C8051F986-GUR Silicon Labs, C8051F986-GUR Datasheet - Page 253

• Manufacturer Part Number: C8051F986-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 512B RAM 12b ADC
• Manufacturer: Silicon Labs

Specifications of C8051F986-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

1100
1000
1110
Values Read
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled
0
0
0
0
0
0 X
0
0
0
0
0
1
1
0
Current SMbus State
A master START was gener-
ated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
A master data byte was
received; ACK sent.
A master data byte was
received; NACK sent (last
byte).
(EHACK = 1)
Rev. 1.1
Typical Response Options
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Set ACK for next data byte;
Read SMB0DAT.
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
Read SMB0DAT; send STOP.
Read SMB0DAT; Send STOP
followed by START.
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
C8051F99x-C8051F98x
Values to
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
Write
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X
0 1
0 1
0 0
0 0
0 X 1100
1 0
1 0
0 0
0 X 1100
1000
1000
1000
1110
1110
1110
1110
1110
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