C8051F996-GUR Silicon Labs, C8051F996-GUR Datasheet - Page 132
C8051F996-GUR
Manufacturer Part Number
C8051F996-GUR
Description
8-bit Microcontrollers - MCU 8kB ADC 14-CH CDC
Manufacturer
Silicon Labs
Datasheet
1.C8051F986-GUR.pdf
(322 pages)
Specifications of C8051F996-GUR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F99x-C8051F98x
12.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been imple-
mented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 12.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 12.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs only accessible from Page 0xF are in bold.
The following procedure should be used when accessing SFRs on Page 0xF:
1. Save the current interrupt state (EA_save = EA).
2. Disable Interrupts (EA = 0).
3. Set SFRPAGE = 0xF.
4. Access the SFRs located on SFR Page 0xF.
5. Set SFRPAGE = 0x0.
6. Restore interrupt state (EA = EA_save).
132
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
(bit addressable)
PSW
ACC
0(8)
P2
P1
P0
IE
B
Table 12.2. Special Function Register (SFR) Memory Map (Page 0xF)
IREF0CF
CLKSEL
P0DRV
1(9)
SP
CRC0CNT
REVID
DPL
2(A)
ADC0PWR
DEVICEID
CS0MD3
P1DRV
DPH
3(B)
Rev. 1.1
CRC0FLIP
CRC0CN
ADC0TK
4(C)
PMU0MD
CRC0IN
P2DRV
TOFFL
FLWR
5(D)
CRC0AUTO
CRC0DAT
CS0PM
TOFFH
EIP1
EIE1
6(E)
SFRPAGE
PCON
EIP2
EIE2
7(F)
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