XRT83L314ES Exar, XRT83L314ES Datasheet - Page 67
![no-image](/images/no-image-200.jpg)
XRT83L314ES
Manufacturer Part Number
XRT83L314ES
Description
LIN Transceivers
Manufacturer
Exar
Datasheet
1.XRT83L314ES.pdf
(84 pages)
Specifications of XRT83L314ES
Product Category
LIN Transceivers
Rohs
yes
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D[6:0]
B
B
D7
D7
D6
D5
D4
D3
D2
IT
IT
8SEG[6:0] Segment Number Eight, Same Description as Register 0x08h
Reserved
Reserved
RCLKE
SR/DR
ATAOS
TCLKE
DATAP
N
N
AME
AME
T
T
ABLE
ABLE
This Register Bit is Not Used
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
Receive Clock Data
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
Transmit Clock Data
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
This Register Bit is Not Used
41: M
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
40: M
ICROPROCESSOR
ICROPROCESSOR
C
HANNEL
G
LOBAL
0-13 (0
F
R
F
UNCTION
UNCTION
EGISTER
R
R
63
EGISTER
EGISTER
X
0F
(0
H
-0
X
E0
0
0
X
DF
X
X
H
0F
E0
)
H
H
)
H
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
XRT83L314
(HW reset)
(HW reset)
Default
Default
REV. 1.0.0
Value
Value
0
0
0
0
0
0
0
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