74LVC1G74DP-G NXP Semiconductors, 74LVC1G74DP-G Datasheet
74LVC1G74DP-G
Specifications of 74LVC1G74DP-G
Related parts for 74LVC1G74DP-G
74LVC1G74DP-G Summary of contents
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Single D-type flip-flop with set and reset; positive edge trigger Rev. 12 — 2 April 2013 1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) ...
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... Marking Table 2. Marking codes Type number 74LVC1G74DP 74LVC1G74DC 74LVC1G74GT 74LVC1G74GF 74LVC1G74GD 74LVC1G74GM 74LVC1G74GN 74LVC1G74GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. ...
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... NXP Semiconductors 5. Functional diagram 001aah757 Fig 1. Logic symbol Fig 3. Logic diagram 74LVC1G74 Product data sheet Single D-type flip-flop with set and reset; positive edge trigger Fig All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC1G74 GND 001aab659 Fig 4. Pin configuration SOT505-2 and SOT765 74LVC1G74 Q 3 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 74LVC1G74 Product data sheet Single D-type flip-flop with set and reset; positive edge trigger ...
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... NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 GND Functional description Table 4. Function table for asynchronous operation Input [ HIGH voltage level; ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +85 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage LOW-level output voltage input leakage current ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = 40 C to +125 C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage LOW-level output voltage input leakage current I I power-off leakage current V ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay see see see pulse width CP HIGH or LOW ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t recovery time SD or RD; see rec set-up time D to CP; see hold time D to CP; see maximum CP ...
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... NXP Semiconductors 12. Waveforms CP input D input Q output Q output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical output voltage levels that occur with the output load Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the set-up, the hold times and the maximum frequency Table 10 ...
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... NXP Semiconductors CP input SD input RD input Q output Q output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 9. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 10. Test circuit for measuring switching times Table 11 ...
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... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.5 mm terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.05 0.35 2.1 mm nom 0.5 min 0.00 0.15 1.9 Outline version IEC SOT996-2 Fig 15. Package outline SOT996-2 (XSON8) 74LVC1G74 Product data sheet Single D-type flip-flop with set and reset ...
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... NXP Semiconductors XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1 terminal 1 index area terminal 1 index area L 1 Dimensions (1) Unit max 0.5 0.05 0.25 1.65 mm nom 0.20 1.60 min 0.00 0.15 1.55 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1116 Fig 17. Package outline SOT1116 (XSON8) ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1203 Fig 18. Package outline SOT1203 (XSON8) ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date 74LVC1G74 v.12 20130402 • Modifications: For type number 74LVC1G74GD XSON8U has changed to XSON8. ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline ...