74LVC1G74DP-G NXP Semiconductors, 74LVC1G74DP-G Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
74LVC1G74DP-G
Manufacturer Part Number
74LVC1G74DP-G
Description
Flip Flops SNGL D-TYPE POSITIVE
Manufacturer
NXP Semiconductors
Datasheet
1.74LVC1G74GM-G.pdf
(25 pages)
Specifications of 74LVC1G74DP-G
Product Category
Flip Flops
Rohs
yes
Number Of Circuits
1
Logic Family
LVC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
3.5 ns at 3.3 V
High Level Output Current
- 32 mA
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-505
Minimum Operating Temperature
- 40 C
Number Of Input Lines
1
Number Of Output Lines
1
Factory Pack Quantity
3000
Supply Voltage - Min
1.65 V
Part # Aliases
74LVC1G74DP,125
NXP Semiconductors
Table 3.
7. Functional description
Table 4.
[1]
Table 5.
[1]
74LVC1G74
Product data sheet
Symbol
CP
D
Q
GND
Q
RD
SD
V
Input
SD
L
H
L
Input
SD
H
H
CC
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
Pin description
Function table for asynchronous operation
Function table for synchronous operation
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1
2
3
4
5
6
7
8
6.2 Pin description
RD
H
L
L
RD
H
H
CP
X
X
X
CP
All information provided in this document is subject to legal disclaimers.
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 12 — 2 April 2013
[1]
[1]
SOT902-2
7
6
5
4
3
2
1
8
D
X
X
X
D
L
H
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
Description
Output
Q
H
L
H
Output
Q
L
H
n+1
74LVC1G74
© NXP B.V. 2013. All rights reserved.
Q
L
H
H
Q
H
L
n+1
5 of 25