XRT83VSH314ES Exar, XRT83VSH314ES Datasheet
XRT83VSH314ES
Specifications of XRT83VSH314ES
Related parts for XRT83VSH314ES
XRT83VSH314ES Summary of contents
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... The LIU features are programmed through a standard microprocessor interface. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT FEATURES • Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications • T1/E1/J1 short haul and clock rate are per port selectable through software without changing components • Internal ...
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REV. 1.0.1 PIN OUT OF THE XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3 XRT83VSH314 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT83VSH314 ........................................................................................................................ 1 IGURE LOCK IAGRAM OF THE ......................................................................................................................................................2 FEATURES PRODUCT ORDERING INFORMATION ..................................................................................................2 PIN OUT OF THE XRT83VSH314 ...................................................................................... ............................................................................................................I ABLE ...
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REV. 1.0.1 4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... ABLE ANDOM IT EQUENCE OLYNOMIALS 4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28 4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 23 ABLE ICROPROCESSOR EGISTER T 24 ............................................................................................................................................. 52 ABLE ABLE ENGTH ETTINGS T 25 ABLE ICROPROCESSOR EGISTER T 26 ABLE ICROPROCESSOR EGISTER T ...
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REV. 1.0.1 1.0 PIN DESCRIPTIONS MICROPROCESSOR AME IN YPE CS A22 I ALE_TS C19 I WR_R/W A20 I RD_WE D18 I RDY_TA AA3 O INT B3 O µPCLK AB2 I 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT D ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT MICROPROCESSOR AME IN YPE ADDR10 A23 I ADDR9 E20 ADDR8 C22 ADDR7 Y18 ADDR6 AA19 ADDR5 AB20 ADDR4 AC21 ADDR3 AB21 ADDR2 AA20 ADDR1 Y19 ADDR0 AC22 DATA7 AA4 I/O ...
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REV. 1.0.1 RECEIVER SECTION AME IN YPE RxON AB19 I RxTSEL Y15 I RLOS AB1 O RCLK13 AB14 O RCLK12 Y22 RCLK11 R22 RCLK10 P22 RCLK9 G22 RCLK8 F22 RCLK7 B14 RCLK6 B9 RCLK5 F2 RCLK4 G2 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION AME IN YPE RCLKOUT K1 O RPOS13 Y14 O RPOS12 W20 RPOS11 P20 RPOS10 N20 RPOS9 H20 RPOS8 G20 RPOS7 D14 RPOS6 D10 RPOS5 G4 RPOS4 H4 RPOS3 ...
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REV. 1.0.1 RECEIVER SECTION AME IN YPE RNEG13 AA14 O RNEG12 Y21 RNEG11 P21 RNEG10 N21 RNEG9 H21 RNEG8 G21 RNEG7 C14 RNEG6 C10 RNEG5 F3 RNEG4 G3 RNEG3 N3 RNEG2 P3 RNEG1 Y3 RNEG0 AA10 RTIP13 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION AME IN YPE TxON AC20 I DMO Y4 O TCLK13 Y16 I TCLK12 Y17 TCLK11 AC18 TCLK10 D16 TCLK9 C17 TCLK8 A19 TCLK7 B16 TCLK6 D7 TCLK5 A3 ...
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REV. 1.0.1 TRANSMITTER SECTION AME IN YPE TNEG13 AC17 I TNEG12 AC19 TNEG11 AA17 TNEG10 B17 TNEG9 B18 TNEG8 C18 TNEG7 C16 TNEG6 C7 TNEG5 D5 TNEG4 C5 TNEG3 C6 TNEG2 AA7 TNEG1 Y7 TNEG0 AB7 TTIP13 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT CONTROL FUNCTION AME IN YPE TEST D4 I ICT A2 I PhDIN L1 I CMPOUT K2 O CLOCK SECTION AME IN YPE MCLKin A6 I 8kHzOUT D8 ...
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REV. 1.0.1 JTAG SECTION AME IN YPE ATP_TIP D21 I/O ATP_RING K21 TMS E4 I TCK B1 I TDI A1 I TDO D3 O 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT D ESCRIPTION Analog Test Pin_TIP Analog Test ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND AME IN YPE TVDD13 AB13 PWR TVDD12 V21 TVDD11 T21 TVDD10 N22 TVDD9 H22 TVDD8 E21 TVDD7 B13 TVDD6 B10 TVDD5 D2 TVDD4 J3 TVDD3 N2 TVDD2 ...
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REV. 1.0.1 POWER AND GROUND AME IN YPE AVDD_BIAS K4 PWR AVDD_PLL22 C15 AVDD_PLL21 B15 AVDD_PLL12 AB16 AVDD_PLL11 AC16 TGND13 Y13 GND TGND12 V20 TGND11 R20 TGND10 M20 TGND9 J20 TGND8 F20 TGND7 D13 TGND6 D11 TGND5 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT POWER AND GROUND AME IN YPE DGND_DRV B2 GND DGND_DRV U3 DGND_DRV A16 DGND_DRV AA8 DGND_DRV AB23 DGND_PRE D15 DGND_PRE AB8 DGND_PRE L20 DGND_UP AB15 AGND_BIAS L3 GND AGND_PLL22 C9 ...
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REV. 1.0.1 2.0 CLOCK SYNTHESIZER In system design, fewer clocks on the network card could reduce noise and interference. Network cards that support both T1 and E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The XRT83VSH314 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A ...
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REV. 1.0.1 RXTSEL TERSEL1 TERSEL0 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT IGURE ECEIVE ATA PDATED ON THE IGURE ECEIVE ATA PDATED ON ...
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REV. 1.0.1 3.2.1 Receive Sensitivity To meet short haul requirements, the XRT83VSH314 can accept T1/E1/J1 signals that have been attenuated by 6dB of cable loss plus 6db of flat loss . Although data integrity is maintained, the RLOS function (if ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.2.3 General Alarm Detection and Interrupt Generation The receive path detects RLOS, AIS, QRPD and FLS. These alarms can be individually masked to prevent the alarm from triggering an interrupt. To enable interrupt ...
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REV. 1.0.1 3.2.3.1 RLOS (Receiver Loss of Signal) The XRT83VSH314supports both G.775 or ETSI-300-233 RLOS detection scheme. In G.775 mode, RLOS is declared when the received signal is less than 375mV for 32 consecutive pulse periods (typical). The device clears ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.3 Jitter Attenuator The jitter attenuator reduces phase and frequency jitter in the recovered clock selected in the receive path. The jitter attenuator uses a data FIFO (First In First ...
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REV. 1.0.1 3.5 RxMUTE (Receiver LOS with Data Muting) The receive muting function can be selected by setting RxMUTE to "1" in the appropriate global register. If selected, any channel that experiences an RLOS condition will automatically pull RPOS and ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A ...
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REV. 1.0 ABLE P ARAMETER TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time (10% to 90%) TCLK Fall Time (90 VDD=3.3V ±5%, VDDc=1.8V ±5%, T OTE 4.2 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.3 Jitter Attenuator The XRT83VSH314 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down ...
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REV. 1.0.1 4.5.1 ATAOS (Automatic Transmit All Ones) If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted for each channel that experiences an RLOS condition. If RLOS does not occur, the ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.6.2 Arbitrary Pulse Generator For T1 and E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming the appropriate channel ...
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REV. 1.0 INE ISTANCE F EET 0 - 133 133 - 266 266 - 399 399 - 525 525 - 655 The same register bank (eight registers in total) holds the values for any given ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.0 T1/E1 APPLICATIONS This applications section describes common T1/E1 system considerations along with references to application notes available for reference where applicable. 5.1 Loopback Diagnostics The XRT83VSH314 supports several loopback modes for diagnostic ...
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REV. 1.0.1 5.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The receive input data at ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.2 84-Channel T1/E1 Multiplexer/Mapper Applications The XRT83VSH314 has the capability of providing the necessary chip selects for multiple 14-channel LIU devices. The LIU is responsible for selecting itself additional LIU ...
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... System designers can achieve this by implementing common redundancy schemes with the XRT83VSH314 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See diagram of the ...
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REV. 1.0.1 5.3.5 Transmit Interface with N+1 Redundancy For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.3.6 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The receivers on the backup card should be programmed for "High" impedance ...
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REV. 1.0.1 5.4 Power Failure Protection For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83VSH314 was ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 5.7 Analog Board Continuity Check This test verifies the per-channel continuity from the Line Side of TIP and RING for both the transmitters and receivers, through the transformers on the assembly and LIU. ...
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REV. 1.0 The Transmitter Line Side uses a 2:1 transformer. OTE 4. If the measured signal is absent, there is either an open or short on the board 1MHz signal applied to the Line Side TTIP ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 6.0 MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (µP) and the LIU. The XRT83VSH314 supports an Intel asynchronous interface, Motorola 68K asynchronous, and a Motorola Power PC ...
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REV. 1.0.1 6.1 The Microprocessor Interface Block Signals The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These interface signals are described below ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 16: M ABLE OTOROLA XRT83VSH314 M OTOROLA T YPE AME QUIVALENT IN ALE_TS TS I WR_R/W R/W I RD_WE Pin OE I µ PCLK ...
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REV. 1.0.1 6.2 Intel Mode Programmed I/O Access (Asynchronous) If the LIU is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel type Read and Write operations are described below. Intel ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 33. I µ IGURE NTEL NTERFACE IGNALS READ OPERATION ALE = ADDR[10:0] Valid Address CS DATA[7: RDY T 17: I ABLE NTEL ...
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REV. 1.0.1 6.3 MPC86X Mode Programmed I/O Access (Synchronous) If the LIU is interfaced to a MPC86X type µP, it should be configured to operate in the MPC86X mode. MPC86X Read and Write operations are described below. MPC86X Mode Read ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT F 34. M MPC86X µP I IGURE OTOROLA TIONS READ OPERATION uPCLK Valid Address ADDR[10:0] CS DATA[7: R 18: M ABLE OTOROLA S P YMBOL ...
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REV. 1.0.1 F 35. M 68K µP I IGURE OTOROLA NTERFACE READ OPERATION _TS ALE t 0 Valid Address ADDR[10: DATA[7: _WE RD _R _DTACK RDY T 19: M ABLE OTOROLA S ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 7.0 REGISTER DESCRIPTIONS T 20: M ABLE R EGISTER DDRESS EX N UMBER 0x00 - 0x0F Channel 0 Control Registers 0x10 - 0x1F Channel ...
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REV. 1.0.1 T 21: M ABLE R ADDR YPE 4 0x04 R/W Reserved DMOIE 5 0x05 RO Reserved DMO 6 0x06 RUR Reserved DMOIS 7 0x07 RO Reserved Reserved 8 0x08 R/W Reserved 1SEG6 9 0x09 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 22: M ABLE R ADDR YPE 239- 0xEF R/W Reserved Reserved 242 0xF2 244 0xF4 R/W Reserved Reserved 245 0xF5 246- 0xF6 R/W Reserved for Reserved for Testing ...
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REV. 1.0.1 T 23: M ABLE AME D5 RxON Receiver ON/OFF Upon power up, the receiver is powered OFF. RxON is used to turn the receiver ON or OFF if the hardware pin RxON is pulled "High". ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 25: M ABLE AME D7 RxTSEL Receive Termination Select Upon power up, the receiver is in "High" impedance. RxTSEL is used to switch between the internal termination and "High" ...
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REV. 1.0.1 T 25: M ABLE AME D1 JABW Jitter Bandwidth (E1 Mode Only permanently set to 3Hz) The jitter bandwidth is a global setting that is applied to both the receiver and transmitter jitter ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 26: M ABLE AME D3 TxOn Transmit ON/OFF Upon power up, the transmitters are powered off. This bit is used to turn the transmitter for this channel On or ...
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REV. 1.0.1 T 27: M ABLE AME D1 INSBER Insert Bit Error When this bit transitions from a "0" "1", a bit error will be inserted in the transmitted QRSS/PRBS pattern. The state of this ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT N : The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the OTE interrupt pin. T 29: M ABLE B ...
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REV. 1.0 The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the OTE interrupt pin. T 29: M ABLE AME D1 RLOS ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 30: M ABLE AME D1 RLOSIS Receiver Loss of Signal Interrupt Status change 1 = Change in status occurred D0 QRPDIS Quasi Random Pattern Detection Interrupt ...
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REV. 1.0.1 T 33: M ABLE AME D7 Reserved This Register Bit is Not Used D[6:0] 2SEG[6:0] Segment Number Two, Same Description as Register 0x08h T 34: M ABLE AME D7 Reserved This Register ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 37: M ABLE AME D7 Reserved This Register Bit is Not Used D[6:0] 6SEG[6:0] Segment Number Six, Same Description as Register 0x08h T 38: M ABLE ...
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REV. 1.0.1 T 40: M ABLE AME D5 RCLKE Receive Clock Data 0 = RPOS/RNEG data is updated on the rising edge of RCLK 1 = RPOS/RNEG data is updated on the falling edge of RCLK D4 ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 41: M ABLE AME D1 EXLOS Extended Loss of Zeros The number of zeros required to declare a Digital Loss of Signal is extended to 4,096 Normal ...
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REV. 1.0.1 T 44: M ABLE AME D7 MCLKT1out1 MCLKT1Nout Select D6 MCLKT1out0 MclkT1out[1:0] is used to program the MCLKT1out pin. By default, the output clock is 1.544MHz 1.544MHz 01 = 3.088MHz 10 = 6.176MHz ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 45: M ABLE AME D4 Reserved This Register Bit is Not Used D3 LCVCH3 Line Code Violation Counter Select D2 LCVCH2 These bits are used to select which channel ...
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REV. 1.0.1 T 46: M ABLE AME D2 BYTEsel LCV Counter Byte Select This bit is used to select the MSB or LSB for Reading the contents of the LCV counter for a given channel. The channel ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 48: M ABLE AME D7 LCVCNT7 Line Code Violation Byte Contents D6 LCVCNT6 These bits contain the LCV counter contents of the Byte selected by bit D2 in register ...
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REV. 1.0.1 T 49: M ABLE AME Reserved These Register Bits are Not Used D4 TCLKCNL Transmit Clock Control When this bit is pulled "High" and there is no TCLK signal present on the ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 50: M ABLE AME D3 GCHIS3 Global Channel Interrupt Status for Channel interrupt activity from channel Interrupt was generated from channel 3 ...
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REV. 1.0 AME D[7:4] Reserved D[3:0] RCLKOUT Recovered Clock Select These register bits are used to select the recovered clock from one of the RCLK[13:0] lines and output it on the RCLKOUT pin. 14-CHANNEL T1/E1/J1 SHORT-HAUL ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT AME D[7:1] Reserved D0 E1Arben E1 Arbitrary Pulse Enable This bit is used to enable the Arbitrary Pulse Generators for shap- ing the transmit pulse shape when E1 mode is ...
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REV. 1.0.1 8.0 ELECTRICAL CHARACTERISTICS Storage Temperature Operating Temperature Supply Voltage Vin T 57 ABLE VDD=3.3V ±5 ARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage IOH=-2.0mA Output Low Voltage IOL=2.0mA Input ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT VDD=3.3V ±5 UPPLY M I ODE MPEDANCE V OLTAGE 75 Ω E1 3.3V 120 Ω E1 3.3V 100 Ω The typical power consumption of the 1.8V supply ...
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REV. 1.0 ABLE VDD = 3. VDD = 1.8V + 5%, IO CORE P ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS ...
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XRT83VSH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT T 62 ABLE VDD=3.3V ±5 ARAMETER Jitter Added by the Transmitter Output Output Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz T 63 ABLE ...
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REV. 1.0.1 ORDERING INFORMATION P N RODUCT UMBER XRT83VSH314IB PACKAGE DIMENSIONS (BOTTOM VIEW SEATING PLANE A1 A SYMBOL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT P ACKAGE 304 LEAD PBGA 304 Ball ...
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... Edited QRSS/PRBS and INVQRSS definition in the register descriptions. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...