MCIMX6S5EVM10AB Freescale Semiconductor, MCIMX6S5EVM10AB Datasheet - Page 11

• Manufacturer Part Number: MCIMX6S5EVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

Freescale Semiconductor
Block Mnemonic
EPIT-1
EPIT-2
EPDC
ENET
ESAI
Electrophoretic Display
Enhanced Serial Audio
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Ethernet Controller
Enhanced Periodic
Interrupt Timer
Block Name
Controller
Interface
Table 2. i.MX 6Solo/6DualLite Modules List (continued)
Timer Peripherals
Subsystem
Connectivity
Connectivity
Peripherals
Peripherals
Peripherals
The Ethernet Media Access Controller (MAC) is
designed to support 10/100/1000 Mbps Ethernet/IEEE
802.3 networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
Note: The theoretical maximum performance of 1 Gbps
ENET is limited to 470 Mbps (total for Tx and Rx) due to
internal bus throughput limitations. The actual
measured performance in optimized environment is up
to 400 Mbps. For details, see the ERR004512 erratum
in the i.MX 6Solo/6DualLite errata document
(IMX6SDLCE).
The EPDC is a feature-rich, low power, and
high-performance direct-drive, active matrix EPD
controller. It is specifically designed to drive E-INK
EPD panels, supporting a wide variety of TFT
backplanes. It is available in both i.MX 6DualLite and
i.MX 6Solo.
Each EPIT is a 32-bit “set and forget” timer that starts
counting after the EPIT is enabled by software. It is
capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a
12-bit prescaler for division of input clock frequency to
get the required time setting for the interrupts to occur,
and counter value can be programmed on the fly.
The Enhanced Serial Audio Interface (ESAI) provides a
full-duplex serial port for serial communication with a
variety of serial devices, including industry-standard
codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and
receiver sections, each section with its own clock
generator. All serial transfers are synchronized to a
clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of
operation is used to transfer data at a periodic rate, one
word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words
(time slots) per period. This mode can be used to build
time division multiplexed (TDM) networks. In contrast,
the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high
speed when the data becomes available.
The ESAI has 12 pins for data and clocking connection
to external devices.
Brief Description
Modules List
™
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