MCIMX6S5EVM10AB Freescale Semiconductor, MCIMX6S5EVM10AB Datasheet - Page 5

• Manufacturer Part Number: MCIMX6S5EVM10AB
• Description: Processors - Application Specialized i.MX6 Solo rev 1.1
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6S5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

The memory system consists of the following components:
Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them
are muxed and not available simultaneously):
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Snoop Control Unit (SCU)
512 KB unified I/D L2 cache:
— Used by one core in i.MX 6Solo
— Shared by two cores in i.MX 6DualLite
Two Master AXI bus interfaces output of L2 cache
Frequency of the core (including Neon and L1 cache), as per
24.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
Level 1 Cache—32 KB Instruction, 32 KB Data cache per core
Level 2 Cache—Unified instruction and data (512 KB)
On-Chip Memory:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
— Secure/non-secure RAM (16 KB)
External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume,
cost effective handheld DRAM, NOR, and NAND Flash memory standards.
— 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and LV-DDR3-800 in i.MX 6Solo;
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
— 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC).
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
— LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example,
— HDMI 1.4 port
16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and LV-DDR3-800, supporting DDR
interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
HD1080 and WXGA at 60 Hz)
WUXGA at 60 Hz) each
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Table 9, "Operating Ranges," on page
Introduction
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