MCIMX6U6AVM08AB Freescale Semiconductor, MCIMX6U6AVM08AB Datasheet - Page 121

• Manufacturer Part Number: MCIMX6U6AVM08AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6U6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 64 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

4.11.13.7 Frame Transmission Mode (Pipelined Data Flow)
4.11.13.8 DATA and FLAG Signal Timing Requirement for a 15 pF Load
Note:
1
2
Freescale Semiconductor
This case shows that the DATA signal has slowed down more compared to the FLAG signal
This case shows that the FLAG signal has slowed down more compared to the DATA signal.
t
TxToRxSkew, maxfq
t
t
EageSepRx, min
EageSepTx, min
t
READY
Rise, min
Parameter
DATA
start bit
FLAG
Frame
t
t
Bit, nom
Fall, min
Figure 84. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)
and
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
DATA
DATA
FLAG
FLAG
(RX)
(RX)
(TX)
(TX)
Description
Channel
Nominal bit time
Minimum allowed rise and fall time
Maximum skew between transmitter and receiver
package pins
Minimum allowed separation of signal transitions at
transmitter package pins, including all timing defects,
for example, jitter and skew, inside the transmitter.
Minimum separation of signal transitions, measured
at the receiver package pins, including all timing
defects, for example, jitter and skew, inside the
receiver.
bits
Complete N-bits Frame
50%
Note1
50%
Note1
t
Bit
Figure 85. DATA and FLAG Signal Timing
t
50%
50%
TxToRxSkew
Table 77. DATA and FLAG Timing
Description
50%
50%
80%
20%
t
Fall
t
Rise
20%
Complete N-bits Frame
80%
t
EdgeSepTx
t
EdgeSepRx
20%
1 Mbit/s
1000 ns
2.00 ns
50.0 ns
400 ns
350 ns
20%
80%
80%
Note2
Note2
100 Mbit/s
0.5.0 ns
10.0 ns
2.00 ns
4.00 ns
3.5 ns
Electrical Characteristics
200 Mbit/s
5.00 ns
1.00 ns
0.25 ns
2.00 ns
1.75 ns
121