MCIMX6U6AVM08AB Freescale Semiconductor, MCIMX6U6AVM08AB Datasheet - Page 67

• Manufacturer Part Number: MCIMX6U6AVM08AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Automotive and Infotainment Processorsr

Specifications of MCIMX6U6AVM08AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 64 bit
• Maximum Clock Frequency: 800 MHz
• Instruction / Data Cache Memory: 32 KB
• Data Ram Size: 128 KB
• Data Rom Size: 96 KB
• Operating Supply Voltage: 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: BGA 2240
• Interface Type: I2S, SSI, AC97, ESAI, UARTS, eCSPI, I2C, Ethernet, PWM, SJC, GPIO, KPP, SPDIF
• Memory Type: DDR3
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Figure 29
1
2
3
4.10
The i.MX 6Solo/6DualLite GPMI controller is a flexible interface NAND Flash controller with 8-bit data
width, up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following subsections.
4.10.1
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in asynchronous mode is about 50 MB/s.
depicts the relative timing between GPMI signals at the module level for different operations under
asynchronous mode.
Freescale Semiconductor
To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle
of DQ window.
All measurements are in reference to Vref level.
Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF.
LP26
ID
DQS (input)
DQ (input)
General-Purpose Media Interface (GPMI) Timing
shows the read timing parameters. The timing parameters for this diagram appear in
CK_B
Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Minimum required DQ valid window width
for LPDDR2
CK
i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors, Rev. 1
Table 51
describes the timing parameters (NF1–NF17) that are shown in the figures.
Parameter
DATA
Figure 29. LPDDR2 Read Cycle
Table 50. LPDDR2 Read Cycle
LP26
DATA
DATA
DATA
DATA
Symbol
Figure 30
—
DATA
Min
270
CK = 400 MHz
through
Electrical Characteristics
DATA
Figure 33
Max
—
DATA
Table
Unit
ps
50.
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