MCIMX6U5DVM10AB Freescale Semiconductor, MCIMX6U5DVM10AB Datasheet - Page 42

• Manufacturer Part Number: MCIMX6U5DVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.7.2
The LPDDR2 interface mode fully complies with JESD209-2B LPDDR2 JEDEC standard release June,
2009. The DDR3/DDR3L interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 29
Table 30
42
AC input logic high
AC input logic low
AC differential input voltage
Input AC differential cross point voltage
Over/undershoot peak
1
2
3
AC input logic high
AC input logic low
AC differential input high voltage
AC differential input low voltage
Input AC differential cross point voltage
Over/undershoot peak
Over/undershoot area (above OVDD
or below OVSS)
Single output slew rate, measured between
Vol(ac) and Voh(ac)
Skew between pad rise/fall asymmetry +
skew caused by SSN
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal
and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD.
Vix(ac) indicates the voltage at which differential input signal must cross.
shows the AC parameters for DDR I/O operating in LPDDR2 mode.
shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
DDR I/O AC Parameters
Parameter
Parameter
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
2
Table 30. DDR I/O DDR3/DDR3L Mode AC Parameters
Table 29. DDR I/O LPDDR2 Mode AC Parameters
2
3
3
Symbol Test Condition
Vih(ac)
Vid(ac)
Vix(ac)
Vil(ac)
Vpeak
Symbol
Vidh(ac)
Vidl(ac)
Vih(ac)
Vix(ac)
Vil(ac)
Vpeak
Varea
t
SKD
tsr
Relative to Vref
Drive impedance = 40
impedance = 60 Ω ±
Test Condition
Relative to Vref
5pF load.Drive
clk = 400 MHz
—
—
—
—
50 Ω to Vref.
50 Ω to Vref.
5 pF load.
400 MHz
Ω ± 30%
30%
—
—
—
—
—
Vref + 0.175
Vref - 0.15
0.35
Min
—
0
Vref + 0.22
-0.12
0.44
Min
1.5
—
—
—
—
0
1
1
Typ
—
—
—
—
—
1
Vref - 0.175
Freescale Semiconductor
Vref - 0.22
Vref + 0.15
OVDD
OVDD
Max
0.44
0.12
0.35
Max
0.3
3.5
2.5
0.1
0.4
—
—
Unit
V-ns
V/ns
ns
V
V
V
V
V
V
Unit
V
V
V
V
V