MCIMX6U5DVM10AB Freescale Semiconductor, MCIMX6U5DVM10AB Datasheet - Page 52

• Manufacturer Part Number: MCIMX6U5DVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
Figure 12
timing parameters mentioned previously for specific control parameters settings.
52
1
In variable latency configuration for write, if BCD = 0 & WBCDD = 1 or BCD = 1, axi_clk must be 104 MHz.Write BCD = 1 and
2
3
WE19 Input Data hold
WE20 WAIT_B setup
WE21 WAIT_B hold time
t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency depends on the fixed/non-fixed
latency configuration, whereas the maximum allowed BCLK frequency is:
—Fixed latency for both read and write is 132 MHz.
—Variable latency for read only is 132 MHz.
—Variable latency for write only is 52 MHz.
104 MHz axi_clk, will result in a BCLK of 52 MHz. When the clock branch to EIM is decreased to 104 MHz, other buses are
impacted which are clocked from this source. See the CCM chapter of the i.MX 6Solo/6DualLite Reference Manual
(IMX6SDLRM) for a detailed clock tree description.
BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
For signal measurements, “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
ID
ADV_B
CSx_B
BEy_B
time from Clock
rise
time to Clock rise
from Clock rise
ADDR
WE_B
OE_B
DATA
BCLK
to
Parameter
Figure 15
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Last Valid Address
provide few examples of basic EIM accesses to external memory devices with the
Figure 12. Synchronous Memory Read Access, WSC=1
Table 39. EIM Bus Timing Parameters (continued)
Min
2
2
2
BCD = 0
Max
—
—
—
WE14
WE10
WE12
WE4
WE6
Min
2
4
2
BCD = 1
Max
WE18
—
—
—
WE15
Address v1
Min
—
—
—
BCD = 2
D(v1)
1
Max
—
—
—
WE11
Freescale Semiconductor
WE7
WE13
WE19
WE5
Min
—
—
—
BCD = 3
Max
—
—
—