IS61WV12816EDBLL-10TLI ISSI, IS61WV12816EDBLL-10TLI Datasheet - Page 10

• Manufacturer Part Number: IS61WV12816EDBLL-10TLI
• Description: SRAM 2Mb (128K x 16) 10ns 2.4V-3.6V
• Manufacturer: ISSI

Specifications of IS61WV12816EDBLL-10TLI

• Rohs: yes
• Memory Size: 2 Mbit
• Organization: 128 Kbit x 16
• Access Time: 10 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V
• Maximum Operating Current: 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-44
• Memory Type: Asynchronous CMOS
• Factory Pack Quantity: 135

IS61/64WV12816EDBLL
10
AC WAVEfORMS
WRITE CYCLE NO. 3
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = Low, UB and/or LB = Low, and WE = LOW. All signals must be in
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
valid states to initiate a Write, but any can be deasserted to terminate the Write. The
to the rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
UB, LB
UB, LB
D
D
OUT
OUT
WE
D
WE
OE
D
CE
OE
CE
IN
IN
LOW
LOW
LOW
DATA UNDEFINED
(WE Controlled. OE is LOW During Write Cycle)
(LB, UB Controlled, Back-to-Back Write)
t
DATA UNDEFINED
SA
t
HZWE
ADDRESS 1
t
SD
t
t
SA
WORD 1
WC
t
PWB
HIGH-Z
DATA
VALID
t
t
AW
HZWE
IN
VALID ADDRESS
t
t
PWE2
t
WC
t
PWB
t
HD
HA
t
HIGH-Z
SA
ADDRESS 2
t
t
SD
Integrated Silicon Solution, Inc. — www.issi.com
DATA
t
SD
(1,3)
WC
WORD 2
t
PWB
IN
DATA
VALID
VALID
(1)
IN
t
HD
t
t
LZWE
t
sa
LZWE
t
,
t
HA
t
HD
t
Ha
HA
,
t
sd
, and
UB_CEWR3.eps
UB_CEWR4.eps
t
Hd
timing is referenced
09/29/2011
Rev. A