C8051F302-GSR Silicon Labs, C8051F302-GSR Datasheet - Page 117
C8051F302-GSR
Manufacturer Part Number
C8051F302-GSR
Description
8-bit Microcontrollers - MCU 8KB 8ADC 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F302-GSR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 13.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 2 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see
to reload while SCL is high, and allow Timer 2 to count when SCL is low. The Timer 2 interrupt service rou-
tine should be used to reset SMBus communication by disabling and reenabling the SMBus. Timer 2 con-
figuration is described in
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 13.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set).
Timer Source
Overflows
SCL
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w
EXTHOLD
Section “13.3.3. SCL Low Timeout” on page
delay occurs between the time SMB0DAT or ACK is written and when SI is cleared.
Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w
delay is zero.
0
1
Table 13.2. Minimum SDA Setup and Hold Times
T
Low
Figure 13.4. Typical SMBus SCL Generation
Section “15.2. Timer 2” on page
Minimum SDA Setup Time
1 system clock + s/w delay
T
low
11 system clocks
– 4 system clocks
T
High
OR
Rev. 2.9
*
151.
114). The SMBus interface will force Timer 2
C8051F300/1/2/3/4/5
Minimum SDA Hold Time
12 system clocks
3 system clocks
SCL High Timeout
117
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