C8051F302-GSR Silicon Labs, C8051F302-GSR Datasheet - Page 123
![no-image](/images/no-image-200.jpg)
C8051F302-GSR
Manufacturer Part Number
C8051F302-GSR
Description
8-bit Microcontrollers - MCU 8KB 8ADC 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F302-GSR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 123 of 178
- Download datasheet (931Kb)
13.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses arbitration or generates a STOP. An SMBus interrupt is generated at the end of
all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating
as a receiver, and after the ACK cycle when operating as a transmitter.
13.5.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates
the START condition and transmits the first byte containing the address of the target slave and the data
direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then transmits
one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the
slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will
switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.
Figure 13.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any
number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK
cycle in this mode.
Figure 13.5. Typical Master Transmitter Sequence
Interrupt
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
W
Interrupt
A
Data Byte
Rev. 2.9
Interrupt
A
C8051F300/1/2/3/4/5
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
Interrupt
A
P
123
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