CY7C1370D-200BGXC Cypress Semiconductor Corp, CY7C1370D-200BGXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1370D-200BGXC
• Description: IC SRAM 18MBIT 200MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-200BGXC

• Memory Size: 18M (512K x 36)
• Package / Case: 119-BGA
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 300 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The data written during the write operation is controlled by BW
(BW
signals. The CY7C1370DV25/CY7C1372DV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1370DV25 and CY7C1372DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The output enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQ
CY7C1372DV25) inputs. Doing so will three-state the output
drivers.
(DQ
CY7C1372DV25) are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1370DV25/CY7C1372DV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in the
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
(BW
inputs must be driven in each cycle of the burst write in order to
write the correct bytes of data.
ZZ Mode Electrical Characteristics
Document Number: 38-05558 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b,c,d
a,b,c,d
a,b,c,d
Parameter
remain
/DQP
/DQP
for CY7C1370DV25 and BW
for CY7C1370DV25 and BW
As
unaltered.
a,b,c,d
a,b,c,d
a
for CY7C1370DV25 and DQ
for CY7C1370DV25 and DQ
safety
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
A
, CE
precaution,
synchronous
2
, and CE
Single Write Accesses
Description
a,b
a,b
3
for CY7C1372DV25)
for CY7C1372DV25)
) and WE inputs are
DQ
self-timed
a,b
a,b
and
/DQP
/DQP
section
a,b
a,b
DQP
write
ZZ  V
ZZ V
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
for
for
DD
DD
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
 0.2 V
Test Conditions
 0.2 V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
11
00
01
10
11
3
, must remain inactive for the duration of t
Address
Second
A1, A0
Address
Second
A1, A0
01
10
11
00
01
00
11
10
2t
DD
Min
CYC
–
–
–
0
Address
A1, A0
Third
)
Address
A1, A0
CY7C1370DV25
CY7C1372DV25
10
00
01
11
Third
10
00
01
11
2t
2t
Max
80
CYC
CYC
–
–
ZZREC
Address
Address
Fourth
A1, A0
Fourth
Page 9 of 29
A1, A0
00
01
10
Unit
11
mA
11
10
01
00
ns
ns
ns
ns
after the
1
, CE
2
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