CY7C1520JV18-300BZXC Cypress Semiconductor Corp, CY7C1520JV18-300BZXC Datasheet - Page 22

• Manufacturer Part Number: CY7C1520JV18-300BZXC
• Description: IC SRAM 72MBIT 300MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520JV18-300BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-12559 Rev. *C
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
Output Times
t
t
t
t
t
t
t
t
t
t
DLL Timing
t
t
t
20. This part has an internal voltage regulator; t
21. These parameters are extrapolated from the input timing parameters (t
22. t
23. At any voltage and temperature t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
CO
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ
CLZ
KC Var
KC lock
KC Reset
Cypress
included in the t
CHZ
, t
CLZ
are specified with a load capacitance of 5 pF as in (b) of
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
CHQX1
KC Var
KC lock
KC Reset
Parameter
KHKH
). These parameters are only guaranteed by design and are not tested in production.
V
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Setup to K Clock Rise
Control Setup to Clock (K, K) Rise (LD, R/W)
Double Data Rate Control Setup to Clock (K, K) Rise (BWS
D
Address Hold after Clock (K and K) Rise
Control Hold after Clock (K and K) Rise (LD, R/W)
Double Data Rate Control Hold after Clock (K and K) Rise (BWS
D
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
Clock (C/C) Rise to High-Z (Active to High-Z)
Clock (C/C) Rise to Low-Z
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
DD
[X:0]
[X:0]
[19]
CHZ
(Typical) to the first Access
Hold after Clock (K and K) Rise
Setup to Clock (K and K) Rise
is less than t
POWER
CLZ
is the time that the power is supplied above V
and t
CHZ
[22, 23]
less than t
[21]
AC Test Loads and
[20]
KHKH
CO
Description
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
.
Waveforms. Transition is measured r100 mV from steady-state voltage.
[22, 23]
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
DD
min initially before a read or write operation can be initiated.
0
, BWS
[21]
0
, BWS
1
, BWS
1
, BWS
2
, BWS
2
, BWS
3
)
3
) 0.3
–0.45
–0.45
–0.27
–0.45
1024
1.32
1.32
1.49
1.24
1.24
Min Max
3.3
0.0
0.4
0.4
0.3
0.3
0.4
0.4
0.3
300 MHz
30
1
–
–
–
–
–
KC Var
Page 22 of 26
1.45
0.45
0.45
0.27
0.45
0.20
8.4
) is already
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Cycles
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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