CY7C1520JV18-300BZXC Cypress Semiconductor Corp, CY7C1520JV18-300BZXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1520JV18-300BZXC
• Description: IC SRAM 72MBIT 300MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520JV18-300BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-12559 Rev. *C
DQ
LD
NWS
NWS
BWS
BWS
BWS
BWS
A, A0
R/W
C
C
K
K
Pin Name
[x:0]
0
1
2
3
0
1
,
,
,
,
Input Output-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input Clock
Input Clock
Input Clock
Input Clock
Input-
Input-
Input-
Input-
Input-
IO
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q
CY7C1516JV18  DQ
CY7C1527JV18  DQ
CY7C1518JV18  DQ
CY7C1520JV18  DQ
Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data.
Nibble Write Select 0, 1  Active LOW (CY7C1516JV18 only). Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which nibble is written into the device during the
current portion of the Write operations. Nibbles not written remain unaltered.
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
Byte Write Select 0, 1, 2, and 3  Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1527JV18  BWS
CY7C1518JV18 BWS
CY7C1520JV18 BWS
D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1516JV18 and 8M x 9 (2 arrays each
of 4M x9) for CY7C1527JV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1518JV18, and 2M x 36 (2
arrays each of 1M x 36) for CY7C1520JV18.
CY7C1516JV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1527JV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1518JV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
22 address inputs are needed to access the entire memory array.
CY7C1520JV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q
[35:27]
0
controls D
.
[3:0]
and NWS
[7:0]
[8:0]
[17:0]
[35:0]
0
0
0
controls D
controls D
controls D
[x:0]
1
when in single clock mode.
[x:0]
controls D
[8:0]
when in single clock mode. All accesses are initiated on the rising
[8:0]
[8:0]
, BWS
and BWS
[x:0]
[7:4]
Pin Description
1
controls D
.
are automatically tri-stated.
1
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
controls D
[17:9]
, BWS
[17:9].
2
controls D
[26:18]
and BWS
Page 6 of 26
3
controls
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