CY7C1520JV18-300BZXC Cypress Semiconductor Corp, CY7C1520JV18-300BZXC Datasheet - Page 7

• Manufacturer Part Number: CY7C1520JV18-300BZXC
• Description: IC SRAM 72MBIT 300MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520JV18-300BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Document Number: 001-12559 Rev. *C
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
V
V
V
V
V
V
Pin Name
SS
SS
REF
DD
SS
DDQ
/144M
/288M
Power Supply Power Supply Inputs to the Core of the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
Input
N/A
IO
(continued)
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DLL Turn Off  Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K: or less pull up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR-I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Ground for the Device.
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
Pin Description
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
DDQ
, which enables the
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