SST25VF032B-80-4I-S2AF Microchip Technology, SST25VF032B-80-4I-S2AF Datasheet
SST25VF032B-80-4I-S2AF
Specifications of SST25VF032B-80-4I-S2AF
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SST25VF032B-80-4I-S2AF Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF032B device is offered in 8-lead SOIC (200 mils) and 8-contact WSON packages. See Figure 2 for pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Note AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page 11 for details FIGURE 1: Functional Block Diagram ©2009 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF032B SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1327 B1.0 S71327-03-000 05/09 ...
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... Mbit SPI Serial Flash SST25VF032B PIN DESCRIPTION CE Top View WP 1327 8-SOIC P1.0 Notes AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of- Write Detection” on page 11 for details. FIGURE 2: Pin Assignments for 8-Lead SOIC ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF032B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... HOLD# Active FIGURE 4: Hold Condition Waveform Write Protection SST25VF032B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... Power- Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. 6 SST25VF032B Read/Write R R R/W R/W R/W R/W R R/W T3.0 1327 S71327-03-000 05/09 ...
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... Lock-Down (BPL) bit. When BPL is set prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. SST25VF032B FOR 2 Status Register Bit BP3 ...
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... Data Sheet INSTRUCTIONS Instructions are used to read, write (Erase and Program), and configure the SST25VF032B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-Enable (WREN) instruction must be executed prior any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Sta- tus-Register, or Chip-Erase instructions ...
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... Mbit SPI Serial Flash SST25VF032B Read (25 MHz) The Read instruction, 03H, supports MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high tran- sition on CE#. The internal address pointer will automati- cally increment until the highest memory address is reached ...
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... The user may poll the Busy bit in the software status register or wait T self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence ADD. ADD. HIGH IMPEDANCE 10 32 Mbit SPI Serial Flash SST25VF032B -A ]. Following the 23 0 for the completion of the internal ADD. IN MSB LSB 1327 F08 ...
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... Mbit SPI Serial Flash SST25VF032B Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when multiple bytes or entire memory array programmed ...
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... Check for Flash Busy Status to load next valid Wait T or poll Software Status BP register to load next valid Mbit SPI Serial Flash SST25VF032B WRDI RDSR n-1 n Last 2 WDRI to exit Data Bytes AAI Mode Wait command Software Status register to load any command 1327 AAI.HW.0 ...
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... Mbit SPI Serial Flash SST25VF032B Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence ...
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... ADDR MSB MSB HIGH IMPEDANCE ADDR ADDR MSB MSB HIGH IMPEDANCE 14 32 Mbit SPI Serial Flash SST25VF032B ), remaining address bits can X CE# must be driven high before the instruction -A ]. Address bits [ are used remaining address bits can X CE# must be driven high before the instruction ...
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... Mbit SPI Serial Flash SST25VF032B Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
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... WRDI instruction. CE# must be driven high before the WRDI instruction is executed. CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1327 F19.0 must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed Mbit SPI Serial Flash SST25VF032B after execut- BP S71327-03-000 05/09 ...
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... Mbit SPI Serial Flash SST25VF032B Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP3, BP2, BP1, BP0, and BPL bits of the status regis- ter. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 19 for EWSR or WREN and WRSR instruction sequences ...
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... Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the device as SST25VF032B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A the Read-ID instruction, the manufacturer’ located in address 00000H and the device ID is located in address ...
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... SST25VF032B JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF032B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 24-bit device ID is shifted out on the SO pin ...
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... CE µA CE µ GND µ GND to V OUT 100 µ 0 1 -100 µ Mbit SPI Serial Flash SST25VF032B +0.5V DD +2. EST = /0.9 V @25 MHz open DD DD /0.9 V @66 MHz open DD DD /0.9 V @80 MHz open Max Max Min DD Max DD ...
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... Mbit SPI Serial Flash SST25VF032B TABLE 10: Capacitance (T = 25° Mhz, other pins open) A Parameter Description 1 C Output Pin Capacitance OUT 1 C Input Capacitance IN 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ...
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... FIGURE 22: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 23: Serial Output Timing Diagram ©2009 Silicon Storage Technology, Inc SCKR T SCKL T OH MSB Mbit SPI Serial Flash SST25VF032B T CPH T T CHS CEH T SCKF LSB HIGH-Z 1327 F23.0 T CHZ LSB 1327 F24.0 S71327-03-000 05/09 ...
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... Mbit SPI Serial Flash SST25VF032B CE# SCK SO SI HOLD# FIGURE 24: Hold Timing Diagram Max DD Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 25: Power-up Timing Diagram ©2009 Silicon Storage Technology, Inc HHS HHH HLS T HLH PU-READ Device fully accessible ...
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... V HT REFERENCE POINTS for a logic “1” and V (0.1V DD ILT DD ) and V (0.4V ). Input rise and fall times (10 Mbit SPI Serial Flash SST25VF032B V HT OUTPUT V LT 1327 IORef.0 ) for a logic “0”. Measurement reference points ↔ 90%) are <5 ns. Note Test HT HIGH Test ...
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... XX XX XXX X - Valid combinations for SST25VF032B SST25VF032B-66-4I-S2AF SST25VF032B-80-4I-S2AF SST25VF032B-80-4I-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2009 Silicon Storage Technology, Inc S2A F ...
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... FIGURE 27: 8-lead Small-outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm) SST Package Code: S2A ©2009 Silicon Storage Technology, Inc. 32 Mbit SPI Serial Flash SIDE VIEW 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 2.16 1.75 0.25 0.19 08-soic-EIAJ-S2A-3 26 SST25VF032B 0˚ 8˚ 0.80 0.50 1mm S71327-03-000 05/09 ...
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... Mbit SPI Serial Flash SST25VF032B TOP VIEW Pin #1 Corner 6.00 ± 0.10 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain V This paddle can be soldered to the PC board; ...
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... Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2009 Silicon Storage Technology, Inc. Description www.SuperFlash.com or www.sst.com 28 32 Mbit SPI Serial Flash SST25VF032B Date Oct 2006 Mar 2008 Jul 2008 May 2009 S71327-03-000 ...