SST25VF032B-80-4I-S2AF Microchip Technology, SST25VF032B-80-4I-S2AF Datasheet - Page 8

• Manufacturer Part Number: SST25VF032B-80-4I-S2AF
• Description: IC FLASH SER 32M 80MHZ SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25VF032B-80-4I-S2AF

• Memory Type: FLASH
• Memory Size: 32M (4M x 8)
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Format - Memory: FLASH
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Bus Width: 8 bit
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Data Sheet
INSTRUCTIONS
Instructions are used to read, write (Erase and Program),
and configure the SST25VF032B. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. The Write-Enable (WREN) instruction must be
executed prior any Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Sta-
tus-Register, or Chip-Erase instructions. The complete list
of instructions is provided in Table 5.
All instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of SCK
starting with the most significant bit. CE# must be driven
TABLE 5: Device Operation Instructions
©2009 Silicon Storage Technology, Inc.
Instruction
Read
High-Speed Read
4 KByte Sector-Erase
32 KByte Block-Erase
64 KByte Block-Erase
Chip-Erase
Byte-Program
AAI-Word-Program
RDSR
EWSR
WRSR
WREN
WRDI
RDID
JEDEC-ID
EBSY
DBSY
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit can be either V
3. 4KByte Sector Erase addresses: use A
4. 32KByte Block Erase addresses: use A
5. 64KByte Block Erase addresses: use A
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A
programmed. Data Byte 0 will be programmed into the initial address [A
initial address [A
device ID output stream is continuous until terminated by a low-to-high transition on CE#.
8
7
6
23
-A
3
4
5
1
] with A
Description
Read Memory
Read Memory at higher speed
Erase 4 KByte of
memory array
Erase 32KByte block
of memory array
Erase 64 KByte block
of memory array
Erase Full Memory Array
To Program One Data Byte
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Register 0101 0000b (50H)
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID read
Enable SO as an output RY/BY#
status during AAI programming
Disable SO as an output RY/BY#
status during AAI programming
0
= 1.
0
= 0, and Device ID is read with A
MS
MS
MS
-A
-A
-A
12,
15,
16,
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
Op Code Cycle
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
0110 0000b (60H) or
1100 0111b (C7H)
0000 0010b (02H)
1010 1101b (ADH)
0000 0101b (05H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
1010 1011b (ABH)
1001 1111b (9FH)
0111 0000b (70H)
1000 0000b (80H)
IL
or V
8
IH
.
0
= 1. All other address bits are 00H. The Manufacturer’s ID and
low before an instruction is entered and must be driven
high after the last bit of the instruction has been shifted in
(except for Read, Read-ID, and Read-Status-Register
instructions). Any low to high transition on CE#, before
receiving the last bit of an instruction bus cycle, will termi-
nate the instruction in progress and return the device to
standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.
23
-A
1
1
] with A
Cycle(s)
0
Address
=0, Data Byte 1 will be programmed into the
3
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
2
32 Mbit SPI Serial Flash
Cycle(s)
Dummy
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IL
Cycle(s)
IL
IL
1 to ∞
1 to ∞
2 to ∞
1 to ∞
1 to ∞
3 to ∞
SST25VF032B
or V
or V
or V
Data
1
0
0
0
0
1
0
0
0
0
0
S71327-03-000
IH.
IH.
IH.
Frequency
Maximum
80 MHz
80 MHz
80 MHz
25 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
T5.0 1327
05/09