ATMEGA16U2-16AU Atmel, ATMEGA16U2-16AU Datasheet - Page 56
ATMEGA16U2-16AU
Manufacturer Part Number
ATMEGA16U2-16AU
Description
8-bit Microcontrollers - MCU 16K Flash
Manufacturer
Atmel
Datasheet
1.ATMEGA16U2-16AU.pdf
(310 pages)
Specifications of ATMEGA16U2-16AU
Product Category
8-bit Microcontrollers - MCU
Rohs
yes
Core
AVR
Data Bus Width
8 bit
Program Memory Size
16 KB
Data Ram Size
1.25 KB
Data Rom Size
512 B
Program Memory Type
Flash
Factory Pack Quantity
1250
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10.5.2
7799D–AVR–11/10
WDTCSR – Watchdog Timer Control Register
• Bit 5 – USBRF: USB Reset Flag
This bit is set if a USB Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 4 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs twice in the Watchdog Timer and if the Watchdog Timer is
configured for interrupt. WDIF is automatically cleared by hardware when executing the corre-
sponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the
flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. Two consecutives
times-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will
clear WDIE and WDIF automatically by hardware : the Watchdog goes to System Reset Mode.
This is useful for keeping the Watchdog Timer security while using the interrupt. To reinitialize
the Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should how-
ever not be done within the interrupt service routine itself, as this might compromise the safety-
Bit
(0x60)
Read/Write
Initial Value
WDIF
R/W
7
0
WDIE
R/W
6
0
WDP3
R/W
5
0
WDCE
R/W
4
0
ATmega8U2/16U2/32U2
WDE
R/W
X
3
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
0
0
WDTCSR
56
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