ATMEGA16U2-16AU Atmel, ATMEGA16U2-16AU Datasheet - Page 88

• Manufacturer Part Number: ATMEGA16U2-16AU
• Description: 8-bit Microcontrollers - MCU 16K Flash
• Manufacturer: Atmel

Specifications of ATMEGA16U2-16AU

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: AVR
• Data Bus Width: 8 bit
• Program Memory Size: 16 KB
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Program Memory Type: Flash
• Factory Pack Quantity: 1250

14. Timer/Counter0 and Timer/Counter1 Prescalers
14.1
14.2
14.3
14.4
7799D–AVR–11/10
Overview
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif-
ferent prescaler settings. The description below applies to all Timer/Counters. Tn is used as a
general name, n = 0 or 1.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by
the Timer/Counter’s clock select, the state of the prescaler will have implications for situations
where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is
enabled and clocked by the prescaler (6 > CSn[2:0] > 1). The number of system clock cycles
from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
= 6) edge it detects.
Figure 14-1. Tn/T0 Pin Sampling
CLK_I/O
/256, or f
Tn
clk
I/O
CLK_I/O
D
LE
/1024.
Q
CLK_I/O
Synchronization
D
). Alternatively, one of four taps from the prescaler can be used
Q
Tn
pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
ATmega8U2/16U2/32U2
clk
D
I/O
). The latch is transparent in the
Q
Figure 14-1
Edge Detector
CLK_I/O
shows a functional
/8, f
Tn_sync
(To Clock
Select Logic)
CLK_I/O
Tn
). The
/64,
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