IS61LPS12836A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61LPS12836A-200TQLI Datasheet - Page 5

• Manufacturer Part Number: IS61LPS12836A-200TQLI
• Description: IC SRAM 4MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Synchronousr

Specifications of IS61LPS12836A-200TQLI

• Memory Size: 4M (128K x 36)
• Package / Case: 100-TQFP, 100-VQFP
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.1 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 210 mA
• Organization: 128 K x 36
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V to 3.3 V
• Density: 4.5Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 210mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1098; IS61LPS12836A-200TQLI

IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
119 BGA PACKAGE PIN CONFIGURATION
256K
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc.
Rev. H
01/07/2010
Note: * A
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
BWE
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
X
18 (TOP VIEW)
0
and A
V
V
V
V
V
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
DQPb
CE2
DQb
DQb
DQb
DQb
V
NC
NC
NC
NC
NC
NC
A
A
A
A
2
DD
MODE
BWb
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
A
A
A
A
3
ADSP
ADSC
BWE
ADV
CLK
GW
V
V
V
OE
A
A
NC
CE
NC
NC
NC
4
DD
DD
DD
1
0
*
*
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
A
A
A
A
5
Symbol
OE
ZZ
MODE
NC
DQa-DQb
DQPa-Pb
V
V
Vss
DD
DDQ
DQPa
DQa
DQa
DQa
DQa
CE2
V
NC
NC
NC
NC
NC
NC
A
A
A
A
6
DD
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
V
V
V
DQa
DQa
V
DQa
DQa
V
NC
NC
NC
NC
ZZ
NC
NC
DDQ
DDQ
DDQ
DDQ
NC
DDQ
7
5