IS61LPS12836A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61LPS12836A-200TQLI Datasheet - Page 6

• Manufacturer Part Number: IS61LPS12836A-200TQLI
• Description: IC SRAM 4MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Synchronousr

Specifications of IS61LPS12836A-200TQLI

• Memory Size: 4M (128K x 36)
• Package / Case: 100-TQFP, 100-VQFP
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.1 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 210 mA
• Organization: 128 K x 36
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V to 3.3 V
• Density: 4.5Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 210mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1098; IS61LPS12836A-200TQLI

IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
165 PBGA PACKAGE PIN CONFIGURATION
128K
PIN DESCRIPTIONS
6
Note: * A
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b,c,d) Synchronous Byte Write
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
X
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
36 (TOP VIEW)
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Controls
3
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
4
BWc
BWd
Vss
V
V
V
V
V
V
V
V
V
Vss
A
A
DD
DD
DD
DD
DD
DD
DD
DD
DD
5
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
A
A
1
0
*
*
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
V
V
Vss
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
DD
DDQ
8
ADSC
OE
Vss
V
V
V
V
V
V
V
V
V
Vss
A
A
DD
DD
DD
DD
DD
DD
DD
DD
DD
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V
Ground
/2.5V
9
ADV
ADSP
V
V
V
V
V
NC
V
V
V
V
V
A
A
Integrated Silicon Solution, Inc.
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
DQPb
DQPa
11
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
A
01/07/2010
Rev. H