IS61LPS12836A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61LPS12836A-200TQLI Datasheet - Page 9

• Manufacturer Part Number: IS61LPS12836A-200TQLI
• Description: IC SRAM 4MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: Synchronousr

Specifications of IS61LPS12836A-200TQLI

• Memory Size: 4M (128K x 36)
• Package / Case: 100-TQFP, 100-VQFP
• Interface: Parallel
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.1 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 210 mA
• Organization: 128 K x 36
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 2.5 V to 3.3 V
• Density: 4.5Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 210mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 706-1098; IS61LPS12836A-200TQLI

IS61(64)LPS12832A
IS61(64)LPS12836A IS61(64)VPS12836A
IS61(64)LPS25618A IS61(64)VPS25618A
PIN CONFIGURATION
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc.
Rev. H
01/07/2010
A0, A1
A
ADSC
ADSP
ADV
BWa-BWb
BWE
CE, CE2, CE2 Synchronous Chip Enable
CLK
DQa-DQb
VDDQ
VDDQ
VDDQ
VDDQ
DQPb
VDD
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100-PIN TQFP (256K X 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3 Chip-Enable Option)
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Controller Address Status
Synchronous Processor Address Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Clock
Synchronous Data Input/Output
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
DQPa-DQPb
GW
MODE
OE
V
V
Vss
ZZ
DD
DDQ
Parity Data I/O; DQPa is parity for
DQa1-8; DQPb is parity for DQb1-8
Synchronous Global Write Enable
Burst Sequence Mode Selection
Output Enable
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Ground
Snooze Enable
9