CY7C1356C-166AXI Cypress Semiconductor Corp, CY7C1356C-166AXI Datasheet - Page 10

• Manufacturer Part Number: CY7C1356C-166AXI
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1356C-166AXI

• Memory Size: 9M (512K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Truth Table
The Truth Table for CY7C1354C and CY7C1356C follows.
Partial Write Cycle Description
The following table lists the Partial Write Cycle Description for CY7C1354C.
Document Number: 38-05538 Rev. *L
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/WRITE ABORT (begin burst)
WRITE ABORT (continue burst)
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Read
Write – no bytes written
Write byte a – (DQ
Write byte b – (DQ
Write bytes b, a
Write byte c – (DQ
Write bytes c, a
Write bytes c, b
Write bytes c, b, a
Write byte d – (DQ
Write bytes d, a
Write bytes d, b
Write bytes d, b, a
Write bytes d, c
Write bytes d, c, a
Write bytes d, c, b
Write all bytes
Notes
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one bytewrite select is active, BWx = valid signifies
3. Write is defined by WE and BWX. See Write Cycle Description table for details.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
that the desired byte write selects are asserted, see Write Cycle Description table for details.
inactive or when the device is deselected, and DQs = data when OE is active.
Function (CY7C1354C)
Operation
c
a
b
d
and DQP
and DQP
and DQP
and DQP
c
b
a
d
)
)
)
)
Address
External
External
External
Current
Used
None
None
None
None
Next
Next
Next
Next
CE ZZ
H
X
X
X
X
X
L
L
L
L
X
X
[2, 3, 4, 5, 6, 7, 8]
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
H
H
H
H
X
X
L
L
L
L
L
X
is valid. Appropriate write will be done based on which byte write is active.
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
[2, 3, 4, 9]
WE BWx
d
H
H
X
X
X
X
X
L
L
X
X
X
X
X
X
X
X
X
H
H
X
X
L
L
BW
CY7C1354C, CY7C1356C
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
OE
H
H
X
X
L
L
X
X
X
X
X
X
c
CEN CLK
H
L
L
L
L
L
L
L
L
L
L
X
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
b
Data out (Q)
Data out (Q)
Data in (D)
Data in (D)
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
DQ
Page 10 of 32
BW
-
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
a
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