CY7C1356C-166AXI Cypress Semiconductor Corp, CY7C1356C-166AXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1356C-166AXI
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1356C-166AXI

• Memory Size: 9M (512K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The data written during the write operation is controlled by BW
(BW
The CY7C1354C/CY7C1356C provides byte write capability that
is described in the Write Cycle Description table. Asserting the
write enable input (WE) with the selected byte write select (BW)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation remain unaltered. A
synchronous self-timed write mechanism is provided to simplify
the write operations. Byte write capability is included to greatly
simplify read/modify/write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1354C and CY7C1356C are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH
(DQ
CY7C1356C) inputs. Doing so will tristate the output drivers. As
a safety precaution, DQ
CY7C1354C
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1354C/CY7C1356C has an on-chip burst counter that
enables the user the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE
and the burst counter is incremented. The correct BW (BW
for CY7C1354C and BW
driven in each cycle of the burst write to write the correct bytes
of data.
Table 3. ZZ Mode Electrical Characteristics
Document Number: 38-05538 Rev. *L
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
a,b,c,d
a,b,c,d
Parameter
before
/DQP
for CY7C1354C and BW
a,b,c,d
and
presenting
1
, CE
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
for CY7C1354C and DQ
DQ
2
, and CE
a,b
a,b
Single Write Accesses on page
/DQP
and DQP
for CY7C1356C) inputs must be
data
a,b
3
Description
) and WE inputs are ignored
a,b
to
for CY7C1356C) signals.
(DQ
for
a,b,c,d
the
CY7C1356C)
/DQP
DQ
a,b
/DQP
a,b,c,d
and
a,b
a,b,c,d
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
DQP
are
for
for
8.
DD
DD
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
Table 1. Interleaved Burst Address Table
(MODE = Floating or V
Table 2. Linear Burst Address Table (MODE = GND)
− 0.2 V
Test Conditions
− 0.2 V
Address
Address
A1, A0
A1, A0
First
First
00
01
10
00
01
10
11
11
3,
must remain inactive for the duration of t
Address
Address
Second
Second
A1, A0
A1, A0
CY7C1354C, CY7C1356C
01
10
11
00
01
00
10
11
DD
)
2t
Min
CYC
–
–
–
0
Address
Address
A1, A0
A1, A0
Third
Third
10
00
01
11
10
11
00
01
2t
2t
Max
50
CYC
CYC
–
–
ZZREC
Address
Address
Fourth
Fourth
A1, A0
A1, A0
Page 9 of 32
Unit
10
01
00
11
00
01
10
11
mA
ns
ns
ns
ns
after the
1
, CE
2
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