CY7C144-55JXC Cypress Semiconductor Corp, CY7C144-55JXC Datasheet - Page 9

• Manufacturer Part Number: CY7C144-55JXC
• Description: IC SRAM 64KBIT 55NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C144-55JXC

• Memory Size: 64K (8K x 8)
• Package / Case: 68-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 160 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2155; CY7C144-55JXC

Switching Characteristics
Over the Operating Range
Document #: 38-06034 Rev. *H
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
t
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
8. At any given temperature and voltage condition for any given device, t
9. Test conditions used are Load 3.
10. This parameter is guaranteed but not tested.
11. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read timing with port-to-port delay waveform.
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
WDD
DDD
[10]
[10]
and 30-pF load capacitance.
Parameter
[11]
[11]
[8, 9,10]
[8, 9,10]
[8, 9,10]
[8, 9,10]
[9,10]
[9,10]
Read cycle time
Address to data valid
Output hold from address change
CE LOW to data valid
OE LOW to data valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
Write pulse width
Data set-up to write end
Data hold from write end
R/W LOW to High Z
R/W HIGH to Low Z
Write pulse to data delay
Write data valid to read data valid
[7]
Description
HZCE
Min
15
15
12
12
12
10

3


3

3

0

2
0
0

3


7C144-15
7C145-15
is less than t
Max
15
15
10
10
10
15
10
30
25














LZCE
and t
HZOE
Min
25
25
20
20
20
15

3


3

3

0

2
0
0

3


7C144-25
is less than t
Max
25
25
15
15
15
25
15
50
30














LZOE
.
CY7C144 CY7C145
Min
55
55
45
45
40
25

3


3

3

0

2
0
0

3


7C144-55
Max
55
55
25
25
25
55
25
70
40














Page 9 of 23
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OI
/I
OH
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