CY7C1418BV18-167BZC Cypress Semiconductor Corp, CY7C1418BV18-167BZC Datasheet
CY7C1418BV18-167BZC
Specifications of CY7C1418BV18-167BZC
Available stocks
Related parts for CY7C1418BV18-167BZC
CY7C1418BV18-167BZC Summary of contents
Page 1
... On CY7C1418BV18 and CY7C1420BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418BV18 and two 36-bit words in the case of CY7C1420BV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ) ...
Page 2
... Logic Block Diagram (CY7C1418BV18) Burst A0 Logic (20:0) A Address (20:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [1:0] Logic Block Diagram (CY7C1420BV18) Burst A0 Logic (19:0) A Address (19:1) Register LD K CLK K Gen. DOFF V REF Control R/W Logic BWS [3:0] Document Number: 001-07033 Rev. *H ...
Page 3
... Pin Configuration The pin configuration for CY7C1418BV18 and CY7C1420BV18 follow NC/72M DQ9 DQ10 DQ11 F NC DQ12 DQ13 H DOFF V V REF DDQ DQ14 L NC DQ15 DQ16 DQ17 R TDO TCK NC/144M DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC DQ31 ...
Page 4
... A, A0 Input- Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each 18) for CY7C1418BV18, and arrays Synchronous each of 512K x 36) for CY7C1420BV18. CY7C1418BV18 – the input to the burst counter. These are incremented in a linear fashion internally. ...
Page 5
... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF measurement points. Reference V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-07033 Rev. *H CY7C1418BV18 CY7C1420BV18 Pin Description Page [+] Feedback ...
Page 6
... Use this feature to simplify read, modify, or write operations to a byte write operation. Single Clock Mode Use the CY7C1418BV18 with a single clock that controls both the input and output registers. In this mode the device recog- nizes only a single pair of input clocks (K and K) that control both the input and output registers ...
Page 7
... DDR I mode (with one cycle latency and a longer access time). For information refer to the application note “DLL Considerations in QDRII™/DDRII”. Figure 1. Application Example R = 250ohms SRAM#1 ZQ CQ/CQ# LD# R/ CY7C1418BV18 CY7C1420BV18 R = 250ohms SRAM CQ/CQ# A LD# R/ Page ...
Page 8
... X = “Don’t Care,” Logic HIGH Logic LOW, 3. Device powers up deselected with the outputs in a tristate condition CY7C1418BV18 and CY7C1420BV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. ...
Page 9
... L–H During the data portion of a write sequence, only the byte (D the device. D remains unaltered. [26:0] – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. CY7C1418BV18 CY7C1420BV18 ) are written into [35:0] ) are written into [35: written ...
Page 10
... TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. CY7C1418BV18 CY7C1420BV18 TAP Controller Block Diagram on ) when ...
Page 11
... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-07033 Rev. *H CY7C1418BV18 CY7C1420BV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation ...
Page 12
... Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-07033 Rev. *H [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1418BV18 CY7C1420BV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
Page 13
... Boundary Scan Register TAP Controller Test Conditions I =2 =100 2 100 GND V /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1418BV18 CY7C1420BV18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD ...
Page 14
... Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-07033 Rev. *H Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50 TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1418BV18 CY7C1420BV18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0.9V t TCYC t TDOX Page ...
Page 15
... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-07033 Rev. *H Value CY7C1420BV18 000 000 11010100010100111 00000110100 00000110100 1 Description CY7C1418BV18 CY7C1420BV18 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size 3 ...
Page 16
... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1418BV18 CY7C1420BV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
Page 17
... SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. . REF Figure 3. Power Up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1418BV18 CY7C1420BV18 . KC Var Start Normal Operation Page [+] Feedback ...
Page 18
... MHz (x18) (x36) (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175 < RQ < 350. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1418BV18 CY7C1420BV18 Test Con- Description Typ Max* ditions Logical 25°C 320 368 Single-Bit Upsets Logical 25° ...
Page 19
... V 250 MHz (x18 1/t , Inputs MAX CYC Static (x36) 200 MHz (x18) (x36) 167 MHz (x18) (x36) Test Conditions CY7C1418BV18 CY7C1420BV18 Min Typ Max Unit 345 mA 370 330 350 300 315 290 300 Min Typ Max Unit V + 0.2 – ...
Page 20
... REF V 0.75V R = 50 REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250 INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1418BV18 CY7C1420BV18 Max Unit = 1. 165 FBGA Unit Package 17.2 °C/W 3.2 °C/W [20] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ns = 0.75V 250 ...
Page 21
... BWS , BWS ) 0.3 – is the time that the power is supplied above V min initially before a read or write operation can be initiated. DD CY7C1418BV18 CY7C1420BV18 250 MHz 200 MHz 167 MHz Unit 1 – 1 – 1 – ms 4.0 8.4 5.0 8.4 6 ...
Page 22
... An input jitter of 200 ps (t KHKH Waveforms. Transition is measured 100 mV from steady-state voltage. AC Test Loads and and t less than t . CLZ CHZ CO CY7C1418BV18 CY7C1420BV18 250 MHz 200 MHz 167 MHz – 0.45 – 0.45 – 0.50 – ...
Page 23
... In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-07033 Rev. *H [26, 27, 28] NOP NOP WRITE WRITE Q00 Q01 Q10 Q11 D20 t CQDOH t CHZ t DOH t CQD CCQO t CQOH t CCQO CY7C1418BV18 CY7C1420BV18 READ D21 D30 Q40 Q41 D31 t KHKH t CYC t CQH t CQHCQH DON’T CARE UNDEFINED Page [+] Feedback ...
Page 24
... Package Type: FPBGA Pb-free Commercial Industrial Speed: 250 MHz Voltage: 1 nm, Errata fix (PCN084656) 36-Mbit DDR II SRAM 2-word burst architecture Technology: CMOS Marketing Code SRAM Company ID Cypress CY7C1418BV18 CY7C1420BV18 and refer to the product summary page at Operating Range Page [+] Feedback ...
Page 25
... Package Diagram Figure 6. 165-ball FBGA ( 1.40 mm), 51-85195 Document Number: 001-07033 Rev. *H CY7C1418BV18 CY7C1420BV18 51-85195 *B Page [+] Feedback ...
Page 26
... Document History Page Document Title: CY7C1418BV18/CY7C1420BV18, 36-Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-07033 Submission Orig. of Rev. ECN No. Date Change ** 433267 See ECN *A 462004 See ECN *B 503690 See ECN *C 1523583 See ECN VKN/AESA Converted from preliminary to final, Updated Logic block diagram, Removed 300 ...
Page 27
... QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. cypress.com/go/plc Revised December 3 , 2010 CY7C1418BV18 CY7C1420BV18 PSoC Solutions psoc.cypress.com/solutions ...