CY7C1418BV18-167BZC Cypress Semiconductor Corp, CY7C1418BV18-167BZC Datasheet - Page 7

• Manufacturer Part Number: CY7C1418BV18-167BZC
• Description: IC SRAM 36MBIT 167MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1418BV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (2M x 18)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ± 15% is between 175 and 350
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
Application Example
Figure 1
Document Number: 001-07033 Rev. *H
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
MASTER
ASIC)
(CPU
BUS
or
shows two DDR II used in an application.
Source CLK#
Return CLK#
Cycle Start#
Return CLK
Source CLK
Addresses
SS
R/W#
DQ
to allow the SRAM to adjust its output
R = 50ohms
DQ
Vterm = 0.75V
Vterm = 0.75V
,
A
with V
LD#
DDQ
SRAM#1
R/W#
Figure 1. Application Example
= 1.5V. The
C C#
CQ/CQ#
K
K#
ZQ
R = 250ohms
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR II. In the single clock mode,
CQ is generated with respect to K, and CQ is generated with
respect to K. The timings for the echo clocks is shown in the AC
Timing Table.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clock K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR I mode (with one cycle
latency and a longer access time). For information refer to the
application note “DLL Considerations in QDRII™/DDRII”.
DQ
A
LD#
SRAM#2
R/W#
CY7C1418BV18
CY7C1420BV18
C C#
CQ/CQ#
K
K#
ZQ
R = 250ohms
Page 7 of 27
[+] Feedback