CYD18S18V18-200BBAXC Cypress Semiconductor Corp, CYD18S18V18-200BBAXC Datasheet - Page 12

• Manufacturer Part Number: CYD18S18V18-200BBAXC
• Description: IC SRAM 18MBIT 200MHZ 256LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S18V18-200BBAXC

• Memory Size: 18M (1M x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-LFBGA
• Memory Configuration: 1M X 18
• Clock Frequency: 77MHz
• Access Time: 3.3ns
• Supply Voltage Range: 1.42V To 1.58V, 1.7V To 1.9V
• Memory Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2036

saved into the busy address register. When a busy readback is performed, the address of the first match that happens at least two
clocks cycles after the busy readback is saved into the busy address register.
Table 3. t
Table 4. Deterministic Access Control Logic
Variable Impedance Matching
Each port contains a variable impedance matching circuit to set
the impedance of the IO driver to match the impedance of the
on-board traces. The impedance is set for all outputs except
JTAG and is done by port. To take advantage of the VIM feature,
connect a calibrating resistor (RQ) that is five times the value of
the intended line impedance from the ZQ
output impedance is then adjusted to account for drifts in supply
voltage and temperature every 1024 clock cycles. If a port’s clock
is suspended, the VIM circuit retains its last setting until the clock
is restarted. On restart, it then resumes periodic adjustment. In
the case of a significant change in device temperature or supply
voltage, recalibration happens every 1024 clock cycles. A master
reset initializes the VIM circuitry.
parameters and
To disable VIM, connect the ZQ pin to VDDIO of the relative
supply for the IOs before a Master Reset.
Document Number: 38-06082 Rev. *J
Port A—Early Arriving Port
Left Port
Mode
Read
Write
Read
Write
SDR
CCS
Timing for All Operating Modes
Table 6
Active Edge
Right Port
Read
Read
Write
Write
C
describes the VIM operation modes.
Left Clock
Port B—Late Arriving Port
> t
< t
> t
< t
> t
Mode
SDR
Table 5
X
CCS
0
CCS
0
CCS
0
CCS
0
0
0
CCS
[1:0]
[25]
shows the VIM
> –t
pin to V
Active Edge
Right Clock
CCS
> t
< t
> t
< t
> t
C
X
0
CCS
0
CCS
0
CCS
0
CCS
CCS
0
SS
& < t
. The
CCS
t
CYC(min)
t
C Rise to Opposite C Rise Setup Time for Non Corrupt Data
CCS
Table 5. Variable Impedance Matching Parameters
Table 6. Variable Impedance Matching Operation
BUSY
RQ value
Output impedance
Reset time
Update time
100 –275  to V
ZQto VDDIO
RQ Connection
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
Parameter
– 0.5
L
BUSY
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
SS
R
Output driver impedance = RQ/5 ± 15%
at Vout = VDDIO/2
VIM disabled. Rout < 20 at Vout =
VDDIO/2
Min
100
N/A
N/A
No collision
Read OLD data
Read NEW data
Read OLD data
Data not guaranteed
Read NEW data
Data Not guaranteed
Read NEW data
Read OLD data
Read NEW data
Data Not guaranteed
Read OLD data
Data not guaranteed
Array data corrupted
Array stores right port data
Array stores left port data
20
Output Configuration
1024
1024
Max
275
55
Description
Cycles
Cycles
Unit


Page 12 of 52
FullFlex
Tolerance
± 15%
± 2%
N/A
N/A
Unit
ns
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