CYD18S18V18-200BBAXC Cypress Semiconductor Corp, CYD18S18V18-200BBAXC Datasheet - Page 17

• Manufacturer Part Number: CYD18S18V18-200BBAXC
• Description: IC SRAM 18MBIT 200MHZ 256LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD18S18V18-200BBAXC

• Memory Size: 18M (1M x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-LFBGA
• Memory Configuration: 1M X 18
• Clock Frequency: 77MHz
• Access Time: 3.3ns
• Supply Voltage Range: 1.42V To 1.58V, 1.7V To 1.9V
• Memory Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2036

Figure 8
Table 8. Interrupt Operation Example
Table 8
Notes
Document Number: 38-06082 Rev. *J
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
32. CE is internal signal. CE = LOW if CE
33. OE is “Don’t Care” for mailbox operation.
34. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
35. The “X” in this diagram represents the counter’s upper bits.
36. “X” = Don’t Care, “H” = HIGH, “L” = LOW.
37. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge.
CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and
CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits.
shows the interrupt operation example.
Function
shows the programmable counter-mask operation with WRP deasserted.
L
Flag
R
L
Flag
Flag
R
Flag
Example:
Load
Counter-Mask
Register = 00007F
Load
Address
Counter = 000005
Max + 1
Address
Value
Max
Address
Value
Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted
R/W
H
L
X
X
L
0
= LOW and CE
CNTINT
CE
X
X
L
L
L
H
H
L
H
2
2
2
2
1
20
20
20
20
= HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is
[32, 33, 34, 36, 37]
Left Port
X
0
X
X
Max Address–1
2
2
2
2
Max Address
19
19
19
19
X
0
X
X
A
Masked Address
0L–20L
X
X
Xs
0s
Xs
Xs
2
2
2
2
7
7
7
7
0
X
X
X
2
2
2
2
INT
6
6
6
6
H
X
X
L
0
1
0
1
2
2
2
2
L
5
5
5
5
0 0
1 1
0 0
1 1
Unmasked Address
2
2
2
2
4
4
4
4
R/W
2
H
[35, 37]
X
L
X
2
2
2
3
3
3
3
R
0
1
0
1
2
2
2
2
2
2
2
2
1
1
1
1
2
CE
2
2
2
1
1
1
1
X
X
L
L
0
1
0
1
R
2
2
2
2
0
0
0
0
1
1
1
1
Right Port
Max Address–1
Max Address
Mask
Register
LSB
Address
Counter
LSB
A
0R–20R
X
X
Page 17 of 52
FullFlex
INT
H
L
X
X
R
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