VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 25

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

UART Transmission in Mode 1
Transmission in this mode is initiated by any
instruction that makes use of SBUF as a destination
register. The 9
is loaded by the “write to SBUF” signal. This event also
flags/informs the TX control unit that a transmission
has been requested.
It is after the next rollover in the divide-by-16 counter
when transmission actually begins. It follows that the
bit times are synchronized to the divide-by-16 counter
and not to the “write to SBUF” signal.
When a transmission begins, it places the Start bit at
TXD. Data transmission is activated one bit time later.
This activation enables the output bit of the transmit
shift register to TXD. One bit time after that, the first
shift pulse occurs.
In this mode, zeros are clocked in from the left as data
bits are shifted out to the right. When the most
significant bit of the data byte is at the output position
of the shift register, the 1 that was initially loaded into
the 9
all positions to the left of that contain zeros. This
condition flags the TX control unit to shift one more
time.
UART Reception in Mode 1
A one to zero transition at pin RXD will initiate
reception. It is for this reason that RXD is sampled at a
rate of 16 multiplied by the baud rate that has been
established. When a transition is detected, 1FFh is
written into the input shift register and the divide-by-16
counter is immediately reset. The divide-by-16 counter
is reset in order to align its rollovers with the
boundaries of the incoming bit times.
In total, there are 16 states in the counter. During the
7
detector samples the value of RXD. The accepted
value is the one seen in at least two of the three
samples. The purpose of doing this is for noise
rejection. If the value accepted during the first bit time
is not zero, the receive circuits are reset and the unit
goes back to searching for another one to zero
transition. All false start bits are rejected by doing this.
If the start bit is valid, it is shifted into the input shift
register, and the reception of the rest of the frame will
proceed.
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th
VRS51C1100
, 8
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th
position is to the immediate left of the MSB and
and 9
th
th
counter states of each bit time, the bit
bit position of the transmit shift register
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register, (9-
bit register), it tells the UART’s receive controller block
to perform one last shift operation: to set RI and to load
SBUF and RB8. The signal to load SBUF and RB8,
and to set RI will be generated if, and only if, the
following conditions are met at the time the final shift
pulse is generated:
If both conditions are met, the stop bit goes into RB8,
the 8 data bits go into SBUF and RI is activated. If one
of these conditions is not met, the received frame is
completely lost. At this time, whether the above
conditions are met or not, the unit returns to searching
for a one to zero transition in RXD.
UART Operation in Mode 2
In Mode 2 a total of 11 bits are transmitted (through
TXD) or received (through RXD). The transactions are
composed of: a Start bit (low), 8 data bits (LSB first), a
programmable 9
For transmission, the 9
bit of SCON. For example, the parity bit P in the PSW
could be moved into TB8.
In the case of receive, the 9
written into RB8 of the SCON register.
o
o
Either SM2 = 0 or the received stop bit = 1
RI = 0
th
data bit and a Stop bit (high).
th
data bit comes from the TB8
th
data bit is automatically
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