VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 27

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

UART in Mode 2 and 3: Additional Information
As mentioned previously, for an operation in modes 2
and 3, 11 bits are transmitted (through TXD) or
received (through RXD). The signal is comprised of: a
logical low Start bit, 8 data bits (LSB first), a
programmable 9
On transmit, (TB8 in SCON) can be assigned the value
of 0 or 1. On receive, the 9
SCON. The baud rate is programmable to either 1/32
or 1/64 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer
1 or Timer 2 depending on the states of TCLK and
RCLK.
UART Transmission in Mode 2 and Mode 3
The transmission is initiated by any instruction that
makes use of SBUF as the destination register. The 9
bit position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also informs the
UART transmission control unit that a transmission has
been requested. After the next rollover in the divide-by-
16 counter, a transmission actually starts at the
beginning of the machine cycle. It follows that the bit
times are synchronized to the divide-by-16 counter and
not to the “write to SBUF” signal, as in the previous
mode.
Transmissions begin when the SEND signal is
activated, which places the Start bit on the TXD pin.
Data is activated one bit time later. This activation
enables the output bit of the transmit shift register to
the TXD pin. The first shift pulse occurs one bit time
after that.
The first shift clocks a Stop bit (1) into the 9
position of the shift register on TXD. Thereafter, only
zeros are clocked in. Thus, as data bits shift out to the
right, zeros are clocked in from the left. When TB8 is at
the output position of the shift register, the stop bit is
just to the left of TB8, and all positions to the left of that
contain zeros. This condition signals to the TX control
unit to shift one more time and set TI, while
deactivating SEND. This occurs at the 11
16 rollover after “write to SBUF”.
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VRS51C1100
th
data bit and a logical high Stop bit.
th
data bit goes into RB8 in
th
divide-by-
th
bit
th
UART Reception in Mode 2 and Mode 3
One to zero transitions on the RXD pin initiate
reception. For this reason the RXD is sampled at a rate
of 16 multiplied by the established baud rate..When a
transition is detected, the 1FFh is written into the input
shift
immediately reset.
During the 7
time, the bit detector samples the value of RXD. The
accepted value is the one seen in at least two of the
three samples. If the value accepted during the first bit
time is not zero, the receive circuits are reset and the
unit goes back to searching for another one to zero
transition. If the Start bit is valid, it is shifted into the
input shift register, and the reception of the rest of the
frame will proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the Start bit
arrives at the leftmost position in the shift register (9-bit
register), it informs the RX control block to do one
more shift, to set RI and to load SBUF and RB8. The
signal to set RI and to load SBUF and RB8 will be
generated if, and only if, the following conditions are
satisfied when the final shift pulse is generated:
If both conditions are met, the 9
goes into RB8, and the first 8 data bits go into SBUF. If
one of these conditions is not met, the received frame
is completely lost. One bit time later, whether the
above conditions are met or not, the unit goes back to
searching for a one to zero transition at the RXD input.
Please note that the value of the received Stop bit is
unrelated to SBUF, RB8 or RI.
-
-
register
Either SM2 = 0 or the received 9
RI = 0
th
, 8
and
th
and 9
the
th
counter states of each bit
divide-by-16
th
data bit received
page 27 of 50
th
bit equal 1
counter
is