VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 35

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Pulse Width Modulation (PWM)
The Pulse Width Modulation (PWM) module consists
of four outputs. Each output uses an 8-bit PWM data
register (PWMD) to set the number of continuous
pulses within a PWM frame cycle.
PWM Function Description:
Each 8-bit PWM output incorporates an 8-bit register
that consists of a 5-bit PWM (5 MSBs) and a 3-bit
(LSBs) narrow pulse generator (NP). The 5-bit PWM
determines the duty cycle of the output. The 3-bit NPx
generates and inserts narrow pulses among the PWM
frame made of 8 cycles.
The number of pulses generated is equal to the
number programmed into the 3-bit NP. The NP is used
to generate an equivalent 8-bit resolution PWM-type
DAC with a reasonably high repetition rate through a 5-
bit PWM clock speed. The PDCK[1:0] settings of the
PWMC (A3h) register are used to derive the PWM
clock from Fosc.
The
(frequency) is calculated using the following formula:
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VRS51C1100
PWM Clock =
PWM Clock =
PWM
output
cycle
32 x 2
2
(PDCK [1:0] +1)
F
F
osc
osc
frame
(PDCK [1:0] +1)
repetition
rate
PWM Output Enable Register
T
PWM Registers -PWM Control Register
The table below describes the PWM control register.
T
The following table describes the relationship between
the values of PDCK1/PDCK0 and the value of the
divider. Numerical values of the corresponding
frequencies are also provided.
ABLE
ABLE
[7:2]
PDCK1
Bit
7:6
1:0
Bit
5
4
3
2
1
0
7
PWM1E
0
0
1
1
38: PWM O
39: PWM C
7
3
Mnemonic
Mnemonic
PWM3E
PWM2E
PWM1E
PWM0E
Unused
6
PDCK1
PDCK0
PDCKO
UTPUT
ONTROL
-
-
0
1
0
1
--
E
5
Unused
NABLE
R
PWM0E
EGISTER
Divider
Description
-
Input Clock Frequency Divider Bit 1
Input Clock Frequency Divider Bit 0
Description
When bit is set to one, the
corresponding PWM pin is active as
a PWM function. When the bit is
cleared, the corresponding PWM pin
is active as an I/O pin. These five
bits are cleared upon reset.
6
2
R
16
2
4
8
EGISTER
4
(PWMC) – SFR A3
(PWME) – SFR 9B
3
Fosc=20MHz
PWM clock,
1.25MHz
PWM3E
2.5MHz
10MHz
5MHz
5
1
H
2
H
page 35 of 50
PDCK1
-
1
Fosc=24MHz
PWM clock,
PWM2E
1.5MHz
12MHz
6MHz
3MHz
4
0
PDCK0
0