ZLF645S2864GP0001 Maxim Integrated, ZLF645S2864GP0001 Datasheet - Page 151

• Manufacturer Part Number: ZLF645S2864GP0001
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S2864GP0001

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Interface Type: UART
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

19-4572; Rev 0; 4/09
Reset/Stop Mode Recovery Status
Fast Stop Mode Recovery
ZLF645 is configured to periodically enter and exit STOP mode until some action is nec-
essary by the application. Follow the steps below to configure the ZLF645 for this mode
of operation:
1. Provide program code that, within 60 processor clock cycles of the start of code exe-
2. Execute the WDT instruction to enable counting of the Watchdog Timer.
3. Include a STOP instruction after the program code for steps 1 & 2 above, that puts the
Once the Watchdog Timer has been enabled through the WDT instruction it will begin
counting and continue counting even after the ZLF645 has entered STOP mode, due to the
bit 3 of the WDTMR register being ‘1’. Once the WDT has reached its time-out value, it
will initiate a reset condition that takes the ZLF645 out of STOP mode. This reset condi-
tion will not cause the WDTMR register to be reset and it will retain its previous program-
ming. Upon completion of the reset the WDT will enter a disabled state and stop counting.
Execution of a new WDT instruction is necessary to cause the Watchdog Timer to reset to
its start count state and to start counting again. It is important to note that if a time-out of
the Watchdog Timer occurs with STOP mode inactive, the reset generated will cause a
reset of the WDTMR register and it will not retain its previously programmed value. In
either case of STOP mode being active or inactive during Watchdog Timer time-out, the
WDT will go to a disabled state upon completion of reset.
Read-only bit SMR[7]=0, if the previous reset was initiated by a Power-On Reset (includ-
ing Voltage Brownout or WDT resets). SMR[7]=1, if the previous reset was initiated by a
Stop Mode Recovery. A power-on, Voltage Brownout, or WDT reset restores all registers
to their Power-On Reset defaults. A Stop Mode Recovery restores most registers to their
Power-On Reset defaults. Register bits not reset by a Stop Mode Recovery are highlighted
in grey in the register tables. Register bit SMR[7] is set to 1 instead of reset by a Stop
Mode Recovery.
SMR[5] can be cleared to 0 before entering STOP mode to bypass the default T
timer on Stop Mode Recovery. See
If SMR[5]=0, the Stop Mode Recovery source must be kept active for at least 10 input
clock periods (TpC).
cution after reset, programs bits 6 through bit 4 and bit 1 through 0 of the Watchdog
Timer Register (WDTMR) with the time-out setting required. Also ensure bit 3 of the
WDTMR register is ‘1’, configuring the WDT for counting once enabled, even with
the ZLF645 in STOP mode.
ZLF645 into STOP mode when no action is required by the ZLF645.
Voltage Brownout Standby
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
on page 139. 
Product Specification
POR
reset
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