ZLF645S2864GP0001 Maxim Integrated, ZLF645S2864GP0001 Datasheet - Page 97
ZLF645S2864GP0001
Manufacturer Part Number
ZLF645S2864GP0001
Description
8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
Manufacturer
Maxim Integrated
Datasheet
1.ZLF645E0H4864G2204.pdf
(201 pages)
Specifications of ZLF645S2864GP0001
Core
Z8
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
64 KB
Data Ram Size
1 KB
Operating Supply Voltage
2 V to 3.6 V
Interface Type
UART
Number Of Programmable I/os
5
Number Of Timers
2 x 8 bit, 1 x 16 bit
Processor Series
ZLF645
Program Memory Type
Flash
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19-4572; Rev 0; 4/09
Caution:
Receiving Data Using the Polled Method
Receiving Data Using the Interrupt-Driven Method
9. Before disabling the transmitter, read the transmit completion status bit, UST[1]. If
Follow the steps below to configure the UART for polled data reception:
1. Write to the BCNST register to set the appropriate baud rate.
2. Write to the UART Control register (UCTL) to:
3. Check the receive status bit in the UART Status register, bit UST[7], to determine if
4. Read data from the UART Receive Data register.
5. Return to
The UART Receiver interrupt indicates the availability of new data (as well as error
conditions).
Follow the steps below to configure the UART receiver for interrupt-driven operation:
1. Write to the UART BRG Constant registers to set the appropriate baud rate.
2. Execute DI instruction to disable interrupts.
3. Write to the Interrupt Control registers to enable the UART receiver interrupt and set
4. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
5. Write to the UART Control register (UCTL) to:
6. Execute an EI instruction to enable interrupts.
Data written while the transmit enable bit is clear (UCTL[7]=0) will not be transmitted.
Data written while the transmit data status bit is clear (UST[2]=0) overwrites the pre-
vious value written, so the previous written value will not be transmitted. Disabling the
UART transmitter while the transmit completion status bit is clear (UST[1]=0) can
corrupt the byte being transmitted.
UST[1]=0, continue to monitor the bit until it changes to 1, which indicates that all
data in the Transmit Data and Internal Shift registers has been transmitted.
(a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception
(b) Enable parity (if appropriate) and select either even- or odd-parity
the Receive Data register contains a valid data byte (indicated by a 1). If UST[7] is set
to 1 to indicate available data, continue to
(indicated by a 0), continue to monitor the UST[7] bit awaiting reception of the valid
data.
the appropriate priority.
(a) Set the receive enable bit (UCTL[6]) to enable the UART for data reception
(b) Enable parity, if appropriate, and select either even- or odd-parity
Step 3
to receive additional data.
Step
4. If the Receive Data register is empty
ZLF645 Series Flash MCUs
Product Specification
Operation
89
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