SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 15

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

FlashFlex MCU
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
3.2.1 Reset Configuration of Program Memory
Block Switching
Program memory block switching is initialized after reset
according to the state of the Start-up Configuration bit SC0
and/or SC1. The SC0 and SC1 bits are programmed via
an external host mode command or an IAP Mode com-
mand. See Table 4-2 and Table 4-7.
Once out of reset, the SFCF[0] bit can be changed dynam-
ically by the program for desired effects. Changing SFCF[0]
will not change the SC0 bit.
Caution must be taken when dynamically changing the
SFCF[0] bit. Since this will cause different physical memory
to be mapped to the logical program address space. The
user must avoid executing block switching instructions
within the address range 0000H to 1FFFH.
TABLE
TABLE
3.3 Data RAM Memory
The data RAM has 1024 bytes of internal memory. The
RAM can be addressed up to 64KB for external data
memory.
©2007 Silicon Storage Technology, Inc.
SC1
U (1)
U (1)
P (0)
P (0)
SC0
U (1)
P (0)
1. P = Programmed (Bit logic state = 0),
1. P = Programmed (Bit logic state = 0),
1
U = Unprogrammed (Bit logic state = 1)
U = Unprogrammed (Bit logic state = 1)
1
SC0
U (1)
P (0)
U (1)
P (0)
3-3: SFCF V
3-4: SFCF V
Power-on
External
(default)
Reset
1
00
01
or
R
R
Power-on
ESET
ESET
External
(default)
Reset
State of SFCF[1:0] after:
00
01
10
11
or
C
C
State of SFCF[1:0] after:
ALUES
ALUES
ONDITIONS
ONDITIONS
WDT Reset
Brown-out
Reset
WDT Reset
Brown-out
or
x0
x1
U
U
NDER
NDER
Reset
x0
x1
10
11
or
(SST89E/V554RC)
(SST89E/V564RD)
D
D
IFFERENT
IFFERENT
Software
Software
Reset
Reset
10
11
T3-3.1 1207
T3-4.1 1207
10
11
10
11
15
3.4 Expanded Data RAM Addressing
The SST89E/V554RC and SSTE/V564RD both have the
capability of 1K of RAM. See Figure 3-3.
The device has four sections of internal data memory:
Since the upper 128 bytes occupy the same addresses as
the SFRs, the RAM must be accessed indirectly. The RAM
and SFRs space are physically separate even though they
have the same addresses.
When instructions access addresses in the upper 128
bytes (above 7FH), the MCU determines whether to
access the SFRs or RAM by the type of instruction given. If
it is indirect, then RAM is accessed. If it is direct, then an
SFR is accessed. See the examples below.
Indirect Access:
Register R0 points to 90H which is located in the upper
address range. Data in “#data” is written to RAM location
90H rather than port 1.
Direct Access:
Data in “#data” is written to port 1. Instructions that write
directly to the address write to the SFRs.
To access the expanded RAM, the EXTRAM bit must be
cleared and MOVX instructions must be used. The extra
768 bytes of memory is physically located on the chip and
logically occupies the first 768 bytes of external memory
(addresses 000H to 2FFH).
When EXTRAM = 0, the expanded RAM is indirectly
addressed using the MOVX instruction in combination
with any of the registers R0, R1 of the selected bank or
DPTR. Accessing the expanded RAM does not affect
ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With
EXTRAM = 0, the expanded RAM can be accessed as
in the following example.
1. The lower 128 Bytes of RAM (00H to 7FH) are
2. The higher 128 Bytes of RAM (80H to FFH) are
3. The special function registers (80H to FFH) are
4. The expanded RAM of 768 Bytes (00H to 2FFH) is
directly and indirectly addressable.
indirectly addressable.
directly addressable only.
indirectly addressable by the move external
instruction (MOVX) and clearing the EXTRAM bit.
(See “Auxiliary Register (AUXR)” in Section 3.6,
“Special Function Registers”)
MOV
MOV
@R0, #data
90H, #data
; R0 contains 90H
; write data to P1
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