SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 38

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

EOL Data Sheet
TABLE
4.2 In-Application Programming Mode
The device offers either 72 or 40 KByte of in-application
programmable flash memory. During in-application pro-
gramming, the CPU of the microcontroller enters IAP
mode. The two blocks of flash memory allow the CPU to
execute user code from one block, while the other is being
erased or reprogrammed concurrently. The CPU may also
fetch code from an external memory while all internal flash
is being reprogrammed. The mailbox registers (SFST,
SFCM, SFAL, SFAH, SFDT and SFCF) located in the spe-
cial function register (SFR), control and monitor the
device’s erase and program process.
Table 4-7 outlines the commands and their associated
mailbox register settings.
4.2.1 In-Application Programming Mode Clock
Source
During IAP mode, both the CPU core and the flash control-
ler unit are driven off the external clock. However, an inter-
nal oscillator will provide timing references for Program and
Erase operations. The internal oscillator is only turned on
when required, and is turned off as soon as the flash oper-
ation is completed.
TABLE
©2007 Silicon Storage Technology, Inc.
1. No operation is performed because code from one block may not program the same originating block
X = Don’t care
EA#
1
1
1
1
1
0
0
0
Address
60H
61H
4-4: A
4-5: IAP A
DDITIONAL
SFCF[1:0]
01, 10, 11
01, 10, 11
01, 10, 11
DDRESS
00
00
00
00
00
R
X
X
EAD
R
ESOLUTION FOR
C
OMMANDS IN
Address of IAP Inst.
>= 2000H (Block 0)
>= 2000H (Block 0)
< 2000H (Block 1)
From external
From external
From external
Any (Block 0)
Any (Block 0)
X
X
SST89E/V564RD
E
XTERNAL
X
X
38
H
4.2.2 Memory Bank Selection for In-Application
Programming Mode
With the addressing range limited to 16 bit, only 64 KByte
of program address space is “visible” at any one time. As
shown in Table 4-5, bank selection (the configuration of
EA# and SFCF[1:0]), allows Block 1 memory to be overlaid
on the lowest 8 KByte of Block 0 memory, making Block 1
reachable. The same concept is employed to allow both
Block 0 and Block 1 flash to be accessible to IAP opera-
tions. Code from a block that is not visible may not be used
as a source to program another address. However, a block
that is not “visible” may be programmed by code from the
other block through mailbox registers.
The device allows IAP code in one block of memory to pro-
gram the other block of memory, but may not program any
location in the same block. If an IAP operation originates
physically from Block 0, the target of this operation is implic-
itly defined to be in Block 1. If the IAP operation originates
physically from Block 1, then the target address is implicitly
defined to be in Block 0. If the IAP operation originates from
external program space, then, the target will depend on the
address and the state of bank selection.
4.2.3 IAP Enable Bit
The IAP enable bit, SFCF[6], enables in-application pro-
gramming mode. Until this bit is set, all flash programming
IAP commands will be ignored.
SC1_i
OST
X
>= 2000H (Block 0)
>= 2000H (Block 0)
>= 2000H (Block 0)
< 2000H (Block 1)
< 2000H (Block 1)
< 2000H (Block 1)
Target Address
M
Any (Block 0)
Any (Block 0)
Data
ODE
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
SC0_i
X
SB1_i
X
Block Being Programmed
FlashFlex MCU
EDC_i
SB2_i
Block 1
Block 0
Block 1
Block 0
Block 1
Block 0
None
None
S71207-08-EOL
1
1
SB3_i
T4-4.4 1207
T4-5.0 1207
X
1/07