FDD14AN06LA0_F085 Fairchild Semiconductor, FDD14AN06LA0_F085 Datasheet - Page 8
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FDD14AN06LA0_F085
Manufacturer Part Number
FDD14AN06LA0_F085
Description
MOSFET 60V N-CHAN PwrTrench
Manufacturer
Fairchild Semiconductor
Datasheet
1.FDD14AN06LA0_F085.pdf
(11 pages)
Specifications of FDD14AN06LA0_F085
Rohs
yes
Transistor Polarity
N-Channel
Drain-source Breakdown Voltage
60 V
Continuous Drain Current
50 A
Resistance Drain-source Rds (on)
12.8 mOhms
Maximum Operating Temperature
+ 175 C
Mounting Style
Through Hole
Package / Case
TO-252AA
Minimum Operating Temperature
- 55 C
Power Dissipation
125 W
Factory Pack Quantity
2500
©2010 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT FDD14AN06LA0 2 1 3 ;
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 28.5e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 64.8
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5e-9
Ldrain 2 5 1.00e-9
Lsource 3 7 2e-9
RLgate 1 9 50
RLdrain 2 5 10
RLsource 3 7 20
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4.2e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 4e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),3))}
.MODEL DbodyMOD D (IS=15e-12 RS=3.2e-3 N=1.05 TRS1=1.5e-3 TRS2=1e-6
+ CJO=10e-10 TT=1.5e-8 M=0.58 IKF=15.00 XTI=3)
.model dbreakmod d (RS=1e-1 TRS1=1.12e-3 TRS2=1.25e-6)
.MODEL DplcapMOD D (CJO=80e-11 IS=1e-30 N=10 M=0.57)
.MODEL MmedMOD NMOS (VTO=2 KP=8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=2.45 KP=105 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.61 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL RbreakMOD RES (TC1=0.92e-3 TC2=-0.35e-6)
.MODEL RdrainMOD RES (TC1=7.92e-3 TC2=3.4e-5)
.MODEL RSLCMOD RES (TC1=2.8E-3 TC2=1E-7)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.5e-3 TC2=-1e-5)
.MODEL RvtempMOD RES (TC1=-2.3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
rev January 2004
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
+
-
MSTRO
14
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
MWEAK
17
RVTHRES
RBREAK
11
+
-
17
18
7
+
18
-
22
RVTEMP
19
RLSOURCE
DBODY
LSOURCE
VBAT
RLDRAIN
LDRAIN
FDD14AN06LA0_F085 Rev. C
SOURCE
DRAIN
2
3