SI1307EDL-T1 Vishay/Siliconix, SI1307EDL-T1 Datasheet - Page 7

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SI1307EDL-T1

Manufacturer Part Number
SI1307EDL-T1
Description
MOSFET 12V 0.91A
Manufacturer
Vishay/Siliconix
Datasheet

Specifications of SI1307EDL-T1

Product Category
MOSFET
Transistor Polarity
P-Channel
Drain-source Breakdown Voltage
12 V
Gate-source Breakdown Voltage
+/- 8 V
Continuous Drain Current
0.85 A
Resistance Drain-source Rds (on)
0.29 Ohms
Configuration
Single
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Package / Case
SOT-323-3
Fall Time
450 ns
Minimum Operating Temperature
- 55 C
Power Dissipation
290 mW
Rise Time
450 ns
Factory Pack Quantity
3000
Typical Turn-off Delay Time
910 ns

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Quantity
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TI
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Part Number:
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INTRODUCTION
This technical note discusses pin-outs, package outlines, pad
patterns, evaluation board layout, and thermal performance
for single-channel LITTLE FOOT power MOSFETs in the
SC-70 package. These new Vishay Siliconix devices are
intended for small-signal applications where a miniaturized
package is needed and low levels of current (around 350 mA)
need to be switched, either directly or by using a level shift
configuration. Vishay provides these single devices with a
range of on-resistance specifications and in both traditional
3-pin and new 6-pin versions. The new 6-pin SC-70 package
enables improved on-resistance values and enhanced
thermal performance compared to the 3-pin package.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the single-channel SC-70 device in both 3-pin and 6-pin
configurations. The pin-out of the 6-pin device allows the use
of four pins as drain leads, which helps to reduce on-resistance
and junction-to-ambient thermal resistance.
For package dimensions see outline drawings:
SC-70 (3-Leads) (http://www.vishay.com/doc?71153)
SC-70 (6-Leads) (http://www.vishay.com/doc?71154)
Document Number: 71236
12-Dec-03
G
S
Single-Channel LITTLE FOOTR SC-70 3-Pin and 6-Pin MOSFET
1
2
SC-70 (3-LEADS)
ChipFETr
Front of Board SC70-3
SOT-323
Top View
Recommended Pad Pattern and Thermal Peformance
3
FIGURE 1.
D
D
D
G
1
2
3
SC-70 (6-LEADS)
SOT-363
Top View
Back of Board, SC70-3 and SC70-6
vishay.com
FIGURE 2.
6
5
4
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the basic
pad layout and dimensions for the 3-pin SC-70 and the 6-pin
SC-70. These pad patterns are sufficient for the low-power
applications for which this package is intended. Increasing the
pad pattern has little effect on thermal resistance for the 3-pin
device, reducing it by only 10% to 15%. But for the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 35% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB). The availability of four drain leads rather than the
traditional single drain lead allows a better thermal path from
the package to the PCB and external environment.
EVALUATION BOARDS FOR THE SINGLE
SC70-3 AND SC70-6
Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards
(EVB). Both measure 0.6 inches by 0.5 inches. Their copper
pad traces are the same as described in the previous section,
Basic Pad Patterns. Both boards allow interrogation from the
outer pins to 6-pin DIP connections, permitting test sockets to
be used in evaluation testing.
The thermal performance of the single SC-70 has been
measured on the EVB for both the 3-pin and 6-pin devices, the
results shown in Figures 3 and 4. The minimum recommended
footprint on the evaluation board was compared with the
industry standard of 1-inch square FR4 PCB with copper on
both sides of the board.
ChipFETr
Front of Board SC70-6
Vishay Siliconix
www.vishay.com
AN813
1

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