P9030-EVK IDT, P9030-EVK Datasheet - Page 24

• Manufacturer Part Number: P9030-EVK
• Description: Power Management IC Development Tools
• Manufacturer: IDT
• Type: PMIC Solutionsr

Specifications of P9030-EVK

• Product: Evaluation Kits
• Tool Is For Evaluation Of: P9030
• Input Voltage: 10 V to 20 V
• Output Voltage: 5 V
• Output Current: 1.5 A
• Part # Aliases: IDTP9030-EVK
• For Use With: P9030-0NTGI

IDTP9030
Product Datasheet
capacitors must be used close to the IN pins of the device.
Since the operating voltage is 18V to 20V, the value of the
capacitors will decrease due to voltage derating
characteristics. For example, a 22μF X7R 25V capacitor’s
value is actually 6μF when operating at 20V.
There must also be an 82μF to 100μF bulk capacitor
connected at the node where the input voltage to the
board is applied.
electrolytic must be connected between the input supply
and ground as shown in Figure 20. Oscon capacitors have
much lower ESR than aluminum electrolytic capacitors
and will reduce voltage ripple.
ADC Considerations
The GPIO pins are connected internally to a successive
approximation ADC with a multiplexed input. The GPIO
pins that are connected to the ADC have limited input
range, so attention must be paid to the maximum VIN
(2.5V). 0.01μF decoupling capacitors can be added to the
GPIO inputs to minimize noise.
WPC TX-A1 Coil
The SW pin connects to a series-resonance circuit
comprising a WPC Type-A1 coil (~24H) and a series
resonant capacitor (~100nF), as shown in Figures 8 and 9.
The inductor serves as the primary coil in a loosely-
coupled transformer, the secondary of which is the
inductor connected to the power receiver (IDTP9020 or
another receiver).
The TX-A1 power transmitter coil is mounted on a ferrite
shield to reduce EMI. The coil assembly can be mounted
next to the IDTP9030. Either ground plane or grounded
copper shielding can be added beneath the ferrite shield
for added reduction in radiated electrical field emissions.
The coil ground plane/shield must be connected to the
IDTP9030 ground plane by a single trace.
Resonance Capacitors
The resonance capacitors must be C0G type dielectric
and have a DC rating to 250V. The highest-efficiency
combination is three 33nF in parallel to get the lowest
ESR. Using a single 100nF or two 47nF capacitors is also
an option. The part numbers are shown in Table 6.
Buck Converter
The input capacitors (C
between the power V
capacitor (C
Revision 1.0
OUT
) and power ground must be connected
IN
A 25V Oscon-type or aluminum
and power PGND pins. The output
IN
) must be connected directly
24
together to minimize any DC regulation errors caused by
ground potential differences.
The bootstrap pin requires a small capacitor; connect a
47nF bootstrap capacitor rated above 25V between the
BST pin and the LX pin.
The output-sense connection to the feedback pins must
be separated from any power trace. Connect the output-
sense trace as close as possible to the load point to avoid
additional load regulation errors. Sensing through a high-
current load trace will degrade DC load regulation.
The power traces, including PGND traces, the SW or OUT
traces and the VIN trace must be kept short, direct and
wide to allow large current flow. The inductor connection
to the SW or OUT pins must be as short as possible. Use
several via pads when routing between layers.
LDOs
Input Capacitor
The input capacitors must be located as physically close
as possible to the power pin (LDO2P5V_IN) and power
ground (GND). Ceramic capacitors are recommended for
their higher current operation and small profile. Also,
ceramic capacitors are inherently more capable than are
tantalum capacitors to withstand input current surges from
low impedance sources such as batteries used in portable
devices. Typically, 10V- or 16V-rated capacitors are
required. The recommended external components are
shown in Table 10.
Output Capacitor
For proper load voltage regulation and operational stability,
a capacitor is required on the output of each LDO
(LDO2P5V and LDO5V). The output capacitor must be
placed as close to the device and power (PGND) pins as
possible. Since the LDOs have been designed to function
with very low ESR capacitors, a ceramic capacitor is
recommended for best performance.
PCB Layout Considerations
-
-
For optimum device performance and lowest output
phase noise, the following guidelines must be
observed. Please contact IDT for Gerber files that
contain the recommended board layout.
As for all switching power supplies, especially those
providing high current and using high switching
frequencies, layout is an important design step. If
layout is not carefully done, the regulator could show
© 2012 Integrated Device Technology, Inc.