MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 35

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 26:
Deep Power-Down
Clock Suspend
Burst Read/Single Write
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
Power-Down
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data in the memory array will not be
retained once deep power-down mode is executed. Deep power-down mode is entered
by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the
rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power-
down.
To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of Deep Power-
Down mode, at least 200µs of valid clocks with either NOP or COMMAND INHIBIT com-
mands are applied to the command bus, followed by a full Mobile SDRAM initialization
sequence, is required.
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 27 and Figure 28 on page 37.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation (M9 = 0).
CKE
CLK
All banks idle
Enter power-down mode
t CKS
NOP
Input buffers gated off
35
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Exit power-down mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS). See Figure 24.
256Mb: x16, x32 Mobile SDRAM
> t CKS
NOP
DON’T CARE
©2006 Micron Technology, Inc. All rights reserved.
ACTIVE
t RCD
t RAS
t RC
Operations