MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 5

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1:
General Description
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
256Mb Mobile SDRAM Part Numbering
The Micron
memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 col-
umns by 16 bits. Each of the x32’s 67,108,864-bit banks is organized as 4096 rows by 512
columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BLs) of 1, 2, 4, or 8
locations, or continuous page burst, with a read burst terminate option. An auto pre-
charge function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. It also allows the column address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide seamless high-speed, random-
access operation.
V
1.8V/1.8V
Example Part Number: MT48H8M32LFB5-75LIT
DD
MT48
/V
DDQ
Configuration
16 Meg x 16
8 Meg x 32
®
256Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access
V
V
H
BF
B5
DDQ
DD
/
Package
8 x 9 VFBGA (lead-free)
8 x 13 VFBGA (lead-free)
Configuration
16M16LF
8M32LF
Mobile
5
Package
Micron Technology, Inc., reserves the right to change products or specifications without notice.
–
Speed
256Mb: x16, x32 Mobile SDRAM
-75
-8
Power
Speed Grade
t
t
L
CK = 7.5ns
CK = 8.0ns
Temp.
Power
Standard I
Low I
I T
DD
Operating Temp.
Commercial
Industrial
Revision
2P/I
General Description
©2006 Micron Technology, Inc. All rights reserved.
:G Design Revision
DD
DD
2P/I
7
DD
Revision
7