MT46H8M32LFB5-5 IT:H Micron Technology Inc, MT46H8M32LFB5-5 IT:H Datasheet - Page 22
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MT46H8M32LFB5-5 IT:H
Manufacturer Part Number
MT46H8M32LFB5-5 IT:H
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H16M16LFBF-5H.pdf
(96 pages)
Specifications of MT46H8M32LFB5-5 IT:H
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
180mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 8: I
Notes 1–5, 7, and 12 apply to all parameters/conditions in this table; V
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Parameter/Condition
Self refresh
CKE = LOW;
are stable; Data bus inputs are stable
DD
t
CK =
6 Specifications and Conditions
t
CK (MIN); Address and control inputs
Notes:
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH
12. Values for I
13. Typical values at 25˚C, not a maximum value.
1. All voltages referenced to V
2. Tests for I
3. Timing and I
4. I
5. I
6. MIN (
7. Measurement is taken 500ms after entering into this operating mode to allow settling
8. V
9. I
related specifications and device operation are guaranteed for the full voltage range
specified.
but input timing is still referenced to V
output timing reference voltage level is V
minimum cycle time with the outputs open.
aged at the defined cycle rate.
minimum absolute value for the respective parameter.
ments is the largest multiple of
time for the tester.
From the time the AUTO REFRESH command is registered, CKE must be active at each
rising clock edge until
command period (
ues are estimated.
DD
DD
DD2N
DD
is dependent on output loading and cycle rates. Specified values are obtained with
specifications are tested after the device is properly initialized and values are aver-
must not vary more than 4% if CKE is not active while any bank is active.
t
specifies DQ, DQS, and DM to be driven to a valid high or low logic level.
RC or
DD
DD6
t
characteristics may be conducted at nominal supply voltage levels, but the
DD
RFC) for I
85˚C are guaranteed for the entire temperature range. All other I
tests may use a V
t
RFC [MIN]) else CKE is LOW (for example, during standby).
DD
t
RFC later.
measurements is the smallest multiple of
22
SS
Electrical Specifications – I
.
1/16 array, 85˚C
1/16 array, 45˚C
Full array, 85˚C
Full array, 45˚C
1/2 array, 85˚C
1/2 array, 45˚C
1/4 array, 85˚C
1/4 array, 45˚C
1/8 array, 85˚C
1/8 array, 45˚C
256Mb: x16, x32 Mobile LPDDR SDRAM
t
CK that meets the maximum absolute value for
IL
-to-V
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
/V
IH
DDQ
DDQ
swing of up to 1.5V in the test environment,
DDQ
/2 (or to the crossing point for CK/CK#). The
= 1.70–1.95V
/2.
Symbol
I
I
I
I
I
I
I
I
I
I
DD6A
DD6A
DD6A
DD6A
DD6A
DD6C
DD6C
DD6C
DD6C
DD6C
t
RAS (MAX) for I
©2008 Micron Technology, Inc. All rights reserved.
t
CK that meets the
DD
I
300
190
250
150
230
130
220
120
200
110
DD6
DD
Parameters
measure-
t
DD6
RAS.
Units
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
val-