MT46H8M32LFB5-5 IT:H Micron Technology Inc, MT46H8M32LFB5-5 IT:H Datasheet - Page 6
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MT46H8M32LFB5-5 IT:H
Manufacturer Part Number
MT46H8M32LFB5-5 IT:H
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H16M16LFBF-5H.pdf
(96 pages)
Specifications of MT46H8M32LFB5-5 IT:H
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/5ns
Maximum Clock Rate
200MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
180mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
List of Figures
Figure 1: 256Mb Mobile LPDDR Part Numbering ............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View) ......................................................................................... 11
Figure 5: 90-Ball VFBGA – 8mm x 13mm (Top View) ....................................................................................... 12
Figure 6: 60-Ball VFBGA (8mm x 9mm) .......................................................................................................... 15
Figure 7: 90-Ball VFBGA (8mm x 13mm) ......................................................................................................... 16
Figure 8: Typical Self Refresh Current vs. Temperature ................................................................................... 23
Figure 9: ACTIVE Command .......................................................................................................................... 35
Figure 10: READ Command ........................................................................................................................... 36
Figure 11: WRITE Command ......................................................................................................................... 37
Figure 12: PRECHARGE Command ................................................................................................................ 38
Figure 13: DEEP POWER-DOWN Command .................................................................................................. 39
Figure 14: Simplified State Diagram ............................................................................................................... 45
Figure 15: Initialize and Load Mode Registers ................................................................................................. 47
Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 48
Figure 17: Standard Mode Register Definition ................................................................................................ 49
Figure 18: CAS Latency .................................................................................................................................. 52
Figure 19: Extended Mode Register ................................................................................................................ 53
Figure 20: Status Read Register Timing .......................................................................................................... 55
Figure 21: Status Register Definition .............................................................................................................. 56
Figure 22: READ Burst ................................................................................................................................... 59
Figure 23: Consecutive READ Bursts .............................................................................................................. 60
Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 61
Figure 25: Random Read Accesses ................................................................................................................. 62
Figure 26: Terminating a READ Burst ............................................................................................................. 63
Figure 27: READ-to-WRITE ............................................................................................................................ 64
Figure 28: READ-to-PRECHARGE .................................................................................................................. 65
Figure 29: Data Output Timing –
Figure 30: Data Output Timing –
Figure 31: Data Output Timing –
Figure 32: Data Input Timing ......................................................................................................................... 70
Figure 33: Write – DM Operation ................................................................................................................... 71
Figure 34: WRITE Burst ................................................................................................................................. 72
Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 73
Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 73
Figure 37: Random WRITE Cycles .................................................................................................................. 74
Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 75
Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 76
Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 77
Figure 41: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 78
Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 79
Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 80
Figure 44: Bank Read – With Auto Precharge .................................................................................................. 83
Figure 45: Bank Read – Without Auto Precharge ............................................................................................. 84
Figure 46: Bank Write – With Auto Precharge .................................................................................................. 85
Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 86
Figure 48: Auto Refresh Mode ........................................................................................................................ 87
Figure 49: Self Refresh Mode ......................................................................................................................... 89
Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 90
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
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DQSQ,
AC and
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QH, and Data Valid Window (x16) ................................................... 66
QH, and Data Valid Window (x32) ................................................... 67
DQSCK .......................................................................................... 68
6
256Mb: x16, x32 Mobile LPDDR SDRAM
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