IS42S32800B-6TL ISSI, Integrated Silicon Solution Inc, IS42S32800B-6TL Datasheet - Page 22
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IS42S32800B-6TL
Manufacturer Part Number
IS42S32800B-6TL
Description
IC SDRAM 256MBIT 166MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-6TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32800B-6TL
Manufacturer:
ISSI
Quantity:
3
Company:
Part Number:
IS42S32800B-6TLI
Manufacturer:
ISSI
Quantity:
4
E
IS42S32800B
22
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
* CL is CAS# Latency.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
RRD
RCD
RP
RAS
CK2
CK3
OH
CH
CL
IS
IH
LZ
HZ
WR
CCD
MRS
AC
tCK and tRC.Input signals are changed one time during tCK.
AC Electrical Characteristics (Recommended Operating Conditions)
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to precharge time
(same bank)
Clock cycle time
Access time from CLK
(positive edge)
Data output hold time
Clock high time
Clock low time
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Data output low impedance
Data output high impedance
Write Recovery Time
CAS# to CAS# Delay time
Mode Register Set cycle time
A.C. Parameter
CL* = 2
CL* = 3
2.5/2.5
7.5/10
2.5/2.5
2.0/2.0
60/70
18/20
12/14
42/45
18/20
Min.
2/2.5
6/7
1
1
2
1
2
- 6/7
Integrated Silicon Solution, Inc.
120,000
5.5/5.5
Max.
5.4
5,6,7,8
Unit
CLK
ns
Note
10
10
10
10
9
9
9
9
9
9
9
8
07/21/09
9
Rev. F