IS42S32800B-6TL ISSI, Integrated Silicon Solution Inc, IS42S32800B-6TL Datasheet - Page 8
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IS42S32800B-6TL
Manufacturer Part Number
IS42S32800B-6TL
Description
IC SDRAM 256MBIT 166MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-6TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32800B-6TL
Manufacturer:
ISSI
Quantity:
3
Company:
Part Number:
IS42S32800B-6TLI
Manufacturer:
ISSI
Quantity:
4
IS42S32800B
8
3
4
PrechargeAll command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Don t care,A10 =”H”)
The Precharge All command precharges all the four banks simultaneously and can be issued even if all banks are
not in the active state. All banks are then switched to the idle state.
Read command
(RAS#=”H”,CAS#=”L”,WE#=”H”,BS =Bank,A10 =”L”,A0-A8 =Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active
bank.The bank must be active for at least tRCD(min.) before the Read command is issued.During read bursts,
the valid data-out element from the starting column address will be available following the CAS# latency after the
issue of the Read command.Each subsequent data- out element will be valid by the next positive clock edge (refer
to the following figure).The DQs go into high-impedance at the end of the burst unless other command is initiated.
The burst length,burst sequence,and CAS# latency are determined by the mode register which is already
programmed.A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
Integrated Silicon Solution, Inc.
07/21/09
Rev. F