IS42S32800B-6TL ISSI, Integrated Silicon Solution Inc, IS42S32800B-6TL Datasheet - Page 23
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IS42S32800B-6TL
Manufacturer Part Number
IS42S32800B-6TL
Description
IC SDRAM 256MBIT 166MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32800B-7BL.pdf
(62 pages)
Specifications of IS42S32800B-6TL
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S32800B-6TL
Manufacturer:
ISSI
Quantity:
3
Company:
Part Number:
IS42S32800B-6TLI
Manufacturer:
ISSI
Quantity:
4
6. A.C. Test Conditions
LVTTL Interface
IS42S32800B
(N otes Continued)
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
7.
8.
9.
10. Assumed input rise and fall time t
11. Power up Sequence
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
t
If clock rising time is longer than 1 ns,(t
If t
should be added to the parameter.
Power up must be performed in the following sequence.
1) Power must be applied to V
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same
time.
2) After power-up,a pause of 200 seconds minimum is required.Then,it is recom
mended that DQM is held “HIGH”(V
impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
HZ
R
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
Output
or t
LVTTL A.C. Test Load
F
is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
Z0=
50Ω
DD
T
30pF
and V
50Ω
1.4V
(t
DD
R
&t
R
levels)to ensure DQ output is in high
DDQ
F
/2 -0.5)ns should be added to the parameter.
)=1 ns
(simultaneously)when all input signals are held “NOP”state
1.4V /1.4V
Reference to the Under Output Load
2.4V /0.4V
1ns
1.4V
23